HDLBits练习——Edgedetect

For each bit in an 8-bit vector, detect when the input signal changes from 0 in one clock cycle to 1 the next (similar to positive edge detection). The output bit should be set the cycle after a 0 to 1 transition occurs.

Here are some examples. For clarity, in[1] and pedge[1] are shown separately.

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前言

两个输入，包括一个时钟clk，一个输入信号in；一个输出上升沿检测信号pedge。

代码

module top_module (
    input clk,
    input [7:0] in,