HDLBits练习——Dualedge

You’re familiar with flip-flops that are triggered on the positive edge of the clock, or negative edge of the clock. A dual-edge triggered flip-flop is triggered on both edges of the clock. However, FPGAs don’t have dual-edge triggered flip-flops, and always @(posedge clk or negedge clk) is not accepted as a legal sensitivity list.

Build a circuit that functionally behaves like a dual-edge triggered flip-flop:

(Note: It’s not necessarily perfectly equivalent: The output of flip-flops have no glitches, but a larger combinational circuit that emulates this behaviour might. But we’ll ignore this detail here.)

---

前言

两个输入，包括一个时钟clk，一个输入信号d；一个输出信号q。

代码

module top_module (
    input clk,
    input d,
    output q
);
	reg pos,neg;    
    always@(posedge clk)
        pos<=d^neg;
    always@(negedge clk)
        neg<=d^pos;
    assign q=pos^neg;
endmodule

总结

刚开始想的clk_reverse发现行不通，我们之前知道输入信号的双边采集为in^in_old，但对于时钟的双边采集而言，我们要构造三个异或门，才能保证无论在上升沿还是下降沿，q都延迟一个时钟得到d值。