HDLBits答案之Fsm1

看题目，该状态机是摩尔机，也就是输出与输入无关，仅仅与所在的状态有关。因此输出会在一个完整的时钟周期内保持稳定，即使此时输入信号有变化，输出也不会变化。输入对输出的影响要到下一个时钟周期才能反映出来。这也是 Moore 型状态机的一个重要特点：输入与输出是隔离开来的。这也就说明，输出表达(第三段）时得用组合逻辑，而不是时序逻辑。

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  

    parameter A=0, B=1; 
    reg state, next_state;
    

    
    always @(posedge clk, posedge areset) begin    // This is a sequential always block
        // State flip-flops with asynchronous reset
        if (areset) 
            state<=B;
        else 
            state<=next_state;
    end
    
    always @(*) begin    // This is a combinational always block
        // State transition logic
        case (in) 
              1 : 
                  if (state==B)  
                  next_state=B;
                  else
                  next_state=A;
              0 :
                  if(state==B)
                      next_state=A;
                  else
                      next_state=B;
         default: next_state=B;
        endcase      
    end

    always @(*) begin    // This is a sequential always block
            if (areset)
                out=1;
            else if(state==B)
                out=1;
            else
                out=0;
        end
        

    // Output logic
    // assign out = (state == ...);

endmodule