module top_module (
input clk,
input reset, // Synchronous reset
input s,
input w,
output z
);
parameter S0=0,S1=1,S2=2,S3=3;
reg [1:0] state,next_state;
reg [1:0] counter;
always@(posedge clk) begin
if(reset)
state<=S0;
else
state<=next_state;
end
always@(posedge clk) begin
case(state)
S0: counter=0;
S1: counter=w;
S2: counter=counter+w;
S3: counter=counter+w;
endcase
end
always@(*) begin
case(state)
S0: next_state = s?S1:S0;
S1: next_state = S2; //检测周期第一个时钟
S2: next_state = S3; //检测周期第二个时钟
S3: next_state = S1; //检测周期第三个时钟
endcase
end
always@(*) begin
case(state)
S1: z = (counter==2)?1:0;
default: z=0;
endcase
end
endmodule