Verilog -刷题 Exams/2014 q3fsm

 用了两种方法。

方法一：设置了四个状态

方法二：参考了网友的答案用了counter

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input s,
    input w,
    output z
);  reg [1:0]state,next_state,sum;
    reg check1,check2,check3;
    parameter a=0,b1=1,b2=2,b3=3;
    always@(*)begin 
        case(state)
            a:next_state = s?b1:a;
            b1:next_state = b2;
            b2:next_state = b3;
            b3:next_state = b1;
        endcase
    end
    always@(posedge clk)begin 
        if(reset)state <= a;
        else state <= next_state;
    end
    always@(posedge clk)begin 
        if(reset)sum = 0;
        else begin 
            case(state)
            a:check1=0;
            b1:check1 = w?1:0;
            b2:check2 = w?1:0;
            b3:check3 = w?1:0;
        endcase
        sum = check1+check2+check3;
    end
    end
    assign z = sum==2&state == b1;
endmodule

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input s,
    input w,
    output z
);   reg state,next_state;
    reg [1:0]i,n;
    parameter a=0,b=1;
    always@(*)begin 
        case(state)
            a:next_state <= s?b:a;
            b:next_state <= b;
        endcase
    end
    always@(posedge clk)begin 
        if(reset)i<=0;
        else case(state)
            a:i<=0;
            b:begin if(i<3) i <= i +1;
                else if(i==3) i <=1;
            end
        endcase
    end
    always@(posedge clk)begin 
        if(reset)n <= 0;
        else case(state)
            a:n<=0;
            b:begin if(i<3) n <=n+w;
                else if(i==3)n<=w;
            end
        endcase
    end
    always@(posedge clk)begin 
        if(reset)state <= a;
        else state <= next_state;
    end
    assign z= (i==3&n==2);
            
   
endmodule