HDL Bits Waveform

Sim/circuit1

module top_module (
    input a,
    input b,
    output q );//

    assign q = a&b; // Fix me

endmodule

Sim/circuit2

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//
	
    wire sum;
    assign sum=a+b+c+d;
    assign q = (sum==0) || (sum==2) || (sum==4); // Fix me
    //assign q = (sum%2==0);

endmodule

Sim/circuit3

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//

    assign q = (a|b)&(c|d); // Fix me

endmodule

Sim/circuit4

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//

    assign q = b|c; // Fix me

endmodule

Sim/circuit5

module top_module (
    input [3:0] a,
    input [3:0] b,
    input [3:0] c,
    input [3:0] d,
    input [3:0] e,
    output [3:0] q );
    
    assign q=(c[3:2]==0)?(c[1]?(c[0]?d:a):(c[0]?e:b)):(4'hf);

endmodule

Sim/circuit6

module top_module (
    input [2:0] a,
    output [15:0] q ); 

    always@(*) begin
        case(a)
            3'd0: q=16'h1232;
            3'd1: q=16'haee0;
            3'd2: q=16'h27d4;
            3'd3: q=16'h5a0e;
            3'd4: q=16'h2066;
            3'd5: q=16'h64ce;
            3'd6: q=16'hc526;
            3'd7: q=16'h2f19;
        endcase
    end
endmodule

Sim/circuit7

module top_module (
    input clk,
    input a,
    output q );
    
    always@(posedge clk) begin
      	q<=~a;     
    end

endmodule

Sim/circuit8

module top_module (
    input clock,
    input a,
    output p,
    output q );
    
    assign p=clock?a:q;
    always@(negedge clock) begin
       q<=a; 
    end

endmodule

Sim/circuit9

module top_module (
    input clk,
    input a,
    output [3:0] q );
    
    always@(posedge clk) begin
        if(a)
            q<=4;
        else if(q==6)
            q<=0;
        else
            q<=q+1'b1;
    end

endmodule

Sim/circuit10

module top_module (
    input clk,
    input a,
    input b,
    output q,
    output state  );
    
    always@(posedge clk) begin
        if(a==b)
            state<=a; //借鉴的
    end
    assign q=a&b&state | (~a)&b&(~state) | a&(~b)&(~state) | (~a)&(~b)&state;

endmodule