`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q
);
//*************code***********//
reg data_r;
always@(posedge clk or negedge rst) begin
if(!rst)
data_r <= 1'b0;
else if(data)
data_r <= ~data_r;
else
data_r <= data_r;
end
always@(posedge clk or negedge rst) begin
if(!rst)
q <= 1'b0;
else if(data_r)
q <= ~q;
else
q <= q;
end
//*************code***********//
endmodule