（南京观海微电子）——GH8555在所罗门系列主控屏驱动参考

#ifndef PNL_TABLE_GH8555BL01
#define PNL_TABLE_GH8555BL01

#define FLAG_DELAY            0xFE
#define FLAG_END_OF_TABLE     0xFF   // END OF REGISTERS MARKER

#define H_ACTIVE        (600)
#define H_SYNC_WIDTH    (20)
#define H_BACK_PROCH    (60)
#define H_FRONT_PROCH   (120)
#define H_START         (H_BACK_PROCH+H_SYNC_WIDTH)
#define H_TOTAL         (H_START+H_ACTIVE+H_FRONT_PROCH)

#define V_ACTIVE         (1024)
#define V_SYNC_WIDTH     (8)
#define V_BACK_PROCH     (8)
#define V_FRONT_PROCH    (100)
#define V_START          (V_BACK_PROCH+V_SYNC_WIDTH)
#define V_TOTAL          (V_START+V_ACTIVE+V_FRONT_PROCH)

#define FPS              (60)
#define DCLK             (V_TOTAL*H_TOTAL*FPS/1000/1000)

#if 1
MhalPnlParamConfig_t stPanel_GH8555BL01_600x1024 =
{
    "GH8555BL01", // const char *m_pPanelName;                ///<  PanelName
#if !defined (__aarch64__)
    0,
#endif
    1, //MS_U8 m_bPanelDither :1;                 ///<  PANEL_DITHER, keep the setting
    E_MHAL_PNL_LINK_MIPI_DSI, //MHAL_DISP_ApiPnlLinkType_e m_ePanelLinkType   :4;  ///<  PANEL_LINK

    ///
    // Board related setting
    ///
    0,  //MS_U8 m_bPanelDualPort  :1;              ///<  VOP_21[8], MOD_4A[1],    PANEL_DUAL_PORT, refer to m_bPanelDoubleClk
    0,  //MS_U8 m_bPanelSwapPort  :1;              ///<  MOD_4A[0],               PANEL_SWAP_PORT, refer to "LVDS output app note" A/B channel swap
    0,  //MS_U8 m_bPanelSwapOdd_ML    :1;          ///<  PANEL_SWAP_ODD_ML
    0,  //MS_U8 m_bPanelSwapEven_ML   :1;          ///<  PANEL_SWAP_EVEN_ML
    0,  //MS_U8 m_bPanelSwapOdd_RB    :1;          ///<  PANEL_SWAP_ODD_RB
    0,  //MS_U8 m_bPanelSwapEven_RB   :1;          ///<  PANEL_SWAP_EVEN_RB

    0,  //MS_U8 m_bPanelSwapLVDS_POL  :1;          ///<  MOD_40[5], PANEL_SWAP_LVDS_POL, for differential P/N swap
    0,  //MS_U8 m_bPanelSwapLVDS_CH   :1;          ///<  MOD_40[6], PANEL_SWAP_LVDS_CH, for pair swap
    0,  //MS_U8 m_bPanelPDP10BIT      :1;          ///<  MOD_40[3], PANEL_PDP_10BIT ,for pair swap
    0,  //MS_U8 m_bPanelLVDS_TI_MODE  :1;          ///<  MOD_40[2], PANEL_LVDS_TI_MODE, refer to "LVDS output app note"

    ///
    // For TTL Only
    ///
    0,  //MS_U8 m_ucPanelDCLKDelay;                ///<  PANEL_DCLK_DELAY
    0,  //MS_U8 m_bPanelInvDCLK   :1;              ///<  MOD_4A[4],                   PANEL_INV_DCLK
    0,  //MS_U8 m_bPanelInvDE     :1;              ///<  MOD_4A[2],                   PANEL_INV_DE
    0,  //MS_U8 m_bPanelInvHSync  :1;              ///<  MOD_4A[12],                  PANEL_INV_HSYNC
    0,  //MS_U8 m_bPanelInvVSync  :1;              ///<  MOD_4A[3],                   PANEL_INV_VSYNC

    ///
    // Output driving current setting
    ///
    // driving current setting (0x00=4mA, 0x01=6mA, 0x02=8mA, 0x03=12mA)
    0,  //MS_U8 m_ucPanelDCKLCurrent;              ///<  define PANEL_DCLK_CURRENT
    0,  //MS_U8 m_ucPanelDECurrent;                ///<  define PANEL_DE_CURRENT
    0,  //MS_U8 m_ucPanelODDDataCurrent;           ///<  define PANEL_ODD_DATA_CURRENT
    0,  //MS_U8 m_ucPanelEvenDataCurrent;          ///<  define PANEL_EVEN_DATA_CURRENT

    ///
    // panel on/off timing
    ///
    0,  //MS_U16 m_wPanelOnTiming1;                ///<  time between panel & data while turn on power
    0,  //MS_U16 m_wPanelOnTiming2;                ///<  time between data & back light while turn on power
    0,  //MS_U16 m_wPanelOffTiming1;               ///<  time between back light & data while turn off power
    0,  //MS_U16 m_wPanelOffTiming2;               ///<  time between data & panel while turn off power

    ///
    // panel timing spec.
    ///
    // sync related
    H_SYNC_WIDTH,  //MS_U8 m_ucPanelHSyncWidth;               ///<  VOP_01[7:0], PANEL_HSYNC_WIDTH
    H_BACK_PROCH,  //MS_U8 m_ucPanelHSyncBackPorch;           ///<  PANEL_HSYNC_BACK_PORCH, no register setting, provide value for query only

                                             ///<  not support Manuel VSync Start/End now
                                             ///<  VOP_02[10:0] VSync start = Vtt - VBackPorch - VSyncWidth
                                             ///<  VOP_03[10:0] VSync end = Vtt - VBackPorch
    V_SYNC_WIDTH,  //MS_U8 m_ucPanelVSyncWidth;               ///<  define PANEL_VSYNC_WIDTH
    V_BACK_PROCH,  //MS_U8 m_ucPanelVBackPorch;               ///<  define PANEL_VSYNC_BACK_PORCH

    // DE related
    H_START,  //MS_U16 m_wPanelHStart;                   ///<  VOP_04[11:0], PANEL_HSTART, DE H Start (PANEL_HSYNC_WIDTH + PANEL_HSYNC_BACK_PORCH)
    V_START,  //MS_U16 m_wPanelVStart;                   ///<  VOP_06[11:0], PANEL_VSTART, DE V Start
    H_ACTIVE,  //MS_U16 m_wPanelWidth;                    ///< PANEL_WIDTH, DE width (VOP_05[11:0] = HEnd = HStart + Width - 1)
    V_ACTIVE,  //MS_U16 m_wPanelHeight;                   ///< PANEL_HEIGHT, DE height (VOP_07[11:0], = Vend = VStart + Height - 1)

    // DClk related
    0,  //MS_U16 m_wPanelMaxHTotal;                ///<  PANEL_MAX_HTOTAL. Reserved for future using.
    H_TOTAL,  //MS_U16 m_wPanelHTotal;                   ///<  VOP_0C[11:0], PANEL_HTOTAL
    0,  //MS_U16 m_wPanelMinHTotal;                ///<  PANEL_MIN_HTOTAL. Reserved for future using.

    0,  //MS_U16 m_wPanelMaxVTotal;                ///<  PANEL_MAX_VTOTAL. Reserved for future using.
    V_TOTAL,  //MS_U16 m_wPanelVTotal;                   ///<  VOP_0D[11:0], PANEL_VTOTAL
    0,  //MS_U16 m_wPanelMinVTotal;                ///<  PANEL_MIN_VTOTAL. Reserved for future using.

    0,  //MS_U8 m_dwPanelMaxDCLK;                  ///<  PANEL_MAX_DCLK. Reserved for future using.
    DCLK,  //MS_U8 m_dwPanelDCLK;                     ///<  LPLL_0F[23:0], PANEL_DCLK          ,{0x3100_10[7:0], 0x3100_0F[15:0]}
    0,  //MS_U8 m_dwPanelMinDCLK;                  ///<  PANEL_MIN_DCLK. Reserved for future using.
                                             ///<  spread spectrum
    0x795,  //MS_U16 m_wSpreadSpectrumStep;            ///<  move to board define, no use now.
    0xAB,  //MS_U16 m_wSpreadSpectrumSpan;            ///<  move to board define, no use now.

    0,  //MS_U8 m_ucDimmingCtl;                    ///<  Initial Dimming Value
    0,  //MS_U8 m_ucMaxPWMVal;                     ///<  Max Dimming Value
    0,  //MS_U8 m_ucMinPWMVal;                     ///<  Min Dimming Value

    0,  //MS_U8 m_bPanelDeinterMode   :1;          ///<  define PANEL_DEINTER_MODE,  no use now
    E_MHAL_PNL_ASPECT_RATIO_WIDE,  //MHAL_DISP_PnlAspectRatio_e m_ucPanelAspectRatio; ///<  Panel Aspect Ratio, provide information to upper layer application for aspect ratio setting.
  /*
    *
    * Board related params
    *
    *  If a board ( like BD_MST064C_D01A_S ) swap LVDS TX polarity
    *    : This polarity swap value =
    *      (LVDS_PN_SWAP_H<<8) | LVDS_PN_SWAP_L from board define,
    *  Otherwise
    *    : The value shall set to 0.
    */
    0,  //MS_U16 m_u16LVDSTxSwapValue;
    E_MHAL_PNL_TI_8BIT_MODE,  //MHAL_DISP_ApiPnlTiBitMode_e m_ucTiBitMode;                         ///< MOD_4B[1:0], refer to "LVDS output app note"
    E_MHAL_PNL_OUTPUT_8BIT_MODE,  //MHAL_DISP_ApiPnlOutPutFormatBitMode_e m_ucOutputFormatBitMode;

    0,  //MS_U8 m_bPanelSwapOdd_RG    :1;          ///<  define PANEL_SWAP_ODD_RG
    0,  //MS_U8 m_bPanelSwapEven_RG   :1;          ///<  define PANEL_SWAP_EVEN_RG
    0,  //MS_U8 m_bPanelSwapOdd_GB    :1;          ///<  define PANEL_SWAP_ODD_GB
    0,  //MS_U8 m_bPanelSwapEven_GB   :1;          ///<  define PANEL_SWAP_EVEN_GB

    /**
    *  Others
    */
    0,  //MS_U8 m_bPanelDoubleClk     :1;             ///<  LPLL_03[7], define Double Clock ,LVDS dual mode
    0x0,  //MS_U32 m_dwPanelMaxSET;                     ///<  define PANEL_MAX_SET
    0x0,  //MS_U32 m_dwPanelMinSET;                     ///<  define PANEL_MIN_SET
    E_MHAL_PNL_CHG_VTOTAL,  //MHAL_DISP_ApiPnlOutTimingMode_e m_ucOutTimingMode;   ///<Define which panel output timing change mode is used to change VFreq for same panel
    0,  //MS_U8 m_bPanelNoiseDith     :1;             ///<  PAFRC mixed with noise dither disable
    E_MHAL_PNL_CH_SWAP_2,
    E_MHAL_PNL_CH_SWAP_4,
    E_MHAL_PNL_CH_SWAP_3,
    E_MHAL_PNL_CH_SWAP_1,
    E_MHAL_PNL_CH_SWAP_0,
};

u8 GH8555BL01_CMD[] =
{
    //GH8558BL-01+TRULY6.95(TFT7D0179)600x1024_MIPI 4lane_20231008
    0xee, 0x01, 0x50,        //ENTER PAGE1
    0xea, 0x02, 0x85,0x55,
    0x24, 0x01, 0xa0,        //mirror te
    0x30, 0x01, 0x00,        // bist=1
    0x35, 0x01, 0x00,
    0x50, 0x01, 0x00, 
    0x56, 0x01, 0x83,
    0x7a, 0x01, 0x20,            //
    0x7b, 0x01, 0x00,            // rgb seq
    0x80, 0x01, 0x10, 
    0x90, 0x02, 0x20,0x40,       // ss_tp location
    0x93, 0x01, 0xf8,        //ss chop
    0x95, 0x01, 0x74,  //  74   column invertion
    0x97, 0x01, 0x09,        //smart gip disable 37,07 enable
    0x99, 0x01, 0x10,
    0xee, 0x01, 0x60,         // enter page2
    0x21, 0x01, 0x00, //01
    0x27, 0x01, 0x62,        
    0x2c, 0x01, 0xf9, 
    0x29, 0x01, 0x8a, 
    0x30, 0x01, 0x01,         // 4 LANE
    0x31, 0x01, 0x0f, 
    0x32, 0x01, 0xdc, //d9        //vrs_tldo
    0x33, 0x01, 0xef, //c3
    0x34, 0x01, 0xef, //2f    
    0x3a, 0x01, 0x24, 
    0x3b, 0x01, 0x00,        
    0x3c, 0x01, 0x0b,       //VCOM SET
    0x3d, 0x01, 0x02,       //vgl//02
    0x3e, 0x01, 0x83,      //vgh//A7
    0x42, 0x01, 0x65,       //vspr
    0x43, 0x01, 0x65,       //vsnr
    0x44, 0x01, 0x0b,       //vgh 17V vgl -9.V
    0x46, 0x01, 0x13,      //vgh 17V    vgl -9V
    0x86, 0x01, 0x20, 
    0x89, 0x01, 0x00, 
    0x8a, 0x01, 0xaa,        // blkh,1
    0x91, 0x01, 0x44,        
    0x92, 0x01, 0x33,        //frq_cp1_clk[2:0]
    0x93, 0x01, 0x9f,        //fp7721 power
    0x9a, 0x01, 0x07,        //s_out=600
    0x9b, 0x02, 0x02,0x00,    //vlength=1024
    0x5a, 0x05, 0x00,0x1A,0x2D,0x39,0x3D,        //gamma n 0.4.8.12.20
    0x47, 0x05, 0x00,0x1A,0x2D,0x39,0x3D,      //gamma P0.4.8.12.20
    0x4c, 0x05, 0x4A,0x42,0x53,0x34,0x34,      //28.44.64.96.128.
    0x5f, 0x05, 0x4A,0x42,0x53,0x34,0x34,     //28.44.64.96.128.
    0x64, 0x05, 0x2a,0x12,0x27,0x24,0x33,        //159.191.211.227.235
    0x51, 0x05, 0x43,0x29,0x3d,0x37,0x43,      //159.191.211.227.235
    0x69, 0x04, 0x2f,0x3f,0x4f,0x6f,          //243.247.251.255
    0x56, 0x04, 0x3F,0x4f,0x5f,0x7f,  
    0xee, 0x01, 0x70,
    0x00, 0x04, 0x01,0x05,0x00,0x01,  //
    0x04, 0x04, 0x06,0x0a,0x44,0x01,  //
    0x0C, 0x02, 0x05,0x05,
    0x10, 0x05, 0x06,0x0a,0x00,0x00,0x00,
    0x15, 0x05, 0x00,0x19,0x0c,0x08,0x00,
    0x20, 0x05, 0x02,0x06,0x00,0x00,0x00,
    0x25, 0x05, 0x00,0x15,0x0c,0x07,0x00,
    0x29, 0x02, 0x05,0x05,
    0x45, 0x01, 0x01,
    0x46, 0x05, 0xff,0x00,0x00,0x00,0x50,
    0x4b, 0x01, 0x88,
    0x60, 0x05, 0x3c,0x05,0x07,0x19,0x1d,
    0x65, 0x05, 0x1b,0x1f,0x11,0x11,0x3c,
    0x6a, 0x05, 0x3c,0x3c,0x3c,0x15,0x15,
    0x6f, 0x05, 0x13,0x13,0x17,0x17,0x01,
    0x74, 0x02, 0x03,0x3c,

    0x80, 0x05, 0x3c,0x04,0x06,0x18,0x1c,
    0x85, 0x05, 0x1a,0x1e,0x10,0x10,0x3c,
    0x8a, 0x05, 0x3c,0x3c,0x3c,0x14,0x14,
    0x8f, 0x05, 0x12,0x12,0x16,0x16,0x00,
    0x94, 0x02, 0x02,0x3c,

    0xea, 0x02, 0x00, 0x00,

    0xee, 0x01, 0x00,                     //enter page0
    0x11, 0x00, 0x00,                     //sleep out
    FLAG_DELAY, FLAG_DELAY, 200,
    0x29, 0x00, 0x00,                     //display on
    FLAG_DELAY, FLAG_DELAY, 50,

    FLAG_END_OF_TABLE, FLAG_END_OF_TABLE,
};

#endif 

MhalPnlMipiDsiConfig_t stMipiDsiConfig_GH8555BL01_600x1024 =
{
    //HsTrail HsPrpr HsZero ClkHsPrpr ClkHsExit ClkTrail ClkZero ClkHsPost DaHsExit ContDet
    0x03, 0x04, 0x05, 0x3, 0x05, 0x03, 0x0A, 0x09, 0x05, 0x00,
    //Lpx TaGet TaSure TaGo
    0x10, 0x1a, 0x18, 0x32,

    //Hac, Hpw, Hbp, Hfp, Vac, Vpw, Vbp, Vfp, Bllp, Fps
    H_ACTIVE, H_SYNC_WIDTH, H_BACK_PROCH, H_FRONT_PROCH, V_ACTIVE, V_SYNC_WIDTH, V_BACK_PROCH, V_FRONT_PROCH, 0, FPS,

    E_MHAL_PNL_MIPI_DSI_LANE_4,      // MhalPnlMipiDsiLaneMode_e enLaneNum;
    E_MHAL_PNL_MIPI_DSI_RGB888,      // MhalPnlMipiDsiFormat_e enFormat;
    E_MHAL_PNL_MIPI_DSI_SYNC_PULSE,  // MhalPnlMipiDsiCtrlMode_e enCtrl;

    GH8555BL01_CMD,
    sizeof(GH8555BL01_CMD),

    1, 0x01AF, 0x01B9, 0x80D2, 8,

    0,0,0,0,0,

    E_MHAL_PNL_MIPI_DSI_PACKET_TYPE_GENERIC,
};
#endif //PNL_TABLE_GH8555BL01