timing verification---hold time check

A hold timing check ensures that a flip-flop output value that is changing does not pass through to a capture flip-flop and overwrite its output before the flip-flop has had a chance to capture its original value. This check is based on the hold requirement of a flip-flop. The hold specification of a flip-flop requires that the data being latched should be held stable for a specified amount of time after the active edge of the clock.

The hold check is from one active edge of the clock in the launch flip-flop to the same clock edge at the capture flip-flop.Thus, a hold check is independent of the clock period. The hold check is carried out on each active edge of the clock of the capture flip-flop.

The hold time check is to ensure that the intended data in the capture flipflopis not overwritten. The hold time check verifies that the difference between
these two times (data arrival time and clock arrival time at capture flip-flop) must be larger than the hold time of the capture flip-flop, so that
the previous data on the flip-flop is not overwritten and the data is reliably captured in the flip-flop.

The hold check can be mathematically expressed as:
Tlaunch + Tck2q + Tdp > Tcapture + Thold

The hold checks impose a lower bound or min constraint for paths to the data pin on the capture flip-flop; the fastest path to the D pin of the capture
flip-flop needs to be determined. This implies that the hold checks are always verified using the shortest paths. Thus, the hold checks are typically
performed at the fast timing corner.

Even when there is only one clock in the design, the clock tree can result in the arrival times of the clocks at the launch and capture flip-flops to be substantially
different. To ensure reliable data capture, the clock edge at the capture flip-flop must arrive before the data can change. A hold timing
check ensures that (see Figure 8-11):

• Data from the subsequent launch edge must not be captured by the setup receiving edge.
• Data from the setup launch edge must not be captured by the preceding receiving edge.

These two hold checks are essentially the same if both the launch and capture clock belong to the same clock domain. However, when the launch
and capture clocks are at different frequencies or in different clock domains, the above two conditions may map into different constraints. In
such cases, the worst hold check is the one that is reported. Figure 8-11 shows these two checks pictorially.

UFF0 is the launch flip-flop and UFF1 is the capture flip-flop. The setup check is between the setup launch edge and the setup receiving edge. The subsequent
launch edge must not propagate data so fast that the setup receiving edge does not have time to capture its data reliably. In addition, the setup
launch edge must not propagate data so fast that the preceding receiving edge does not get a chance to capture its data. The worst hold check corresponds

to the most restrictive hold check amongst various scenarios described above.

While setup violations can cause the operating frequency of the design to be lowered, the hold violations can kill a design, that is, make the design
inoperable at any frequency. Thus it is very important to understand the hold timing checks and resolve any violations.

1.Flip-flop to Flip-flop Path

2.Input to Flip-flop Path

set_input_delay -clock VIRTUAL_CLKM \
-min 1.1 [get_ports INA]

Startpoint: INA (input port clocked by VIRTUAL_CLKM)
Endpoint: UFF2 (rising edge-triggered flip-flop clocked by CLKM)

3.Flip-flop to Output Path

set_output_delay -clock VIRTUAL_CLKP \
-min 2.5 [get_ports ROUT]

4.Input to Output Path

set_load -pin_load 0.15 [get_ports POUT]
set_output_delay -clock VIRTUAL_CLKM \
-min 3.2 [get_ports POUT]
set_input_delay -clock VIRTUAL_CLKM \
-min 1.8 [get_ports INB]
set_input_transition 0.8 [get_ports INB]