- 博客(20)
- 资源 (8)
- 收藏
- 关注
RSS订阅转载 综合DC/RC--要点
综合的注意事项Q1.1 需要fix hold吗？不需要，hold交由后端去做就好了。所以综合时，不需要读入min.lib，不用设wc_bc等复杂的选项Q1.2 综合出来的网表如何验证？如RTL做形式验证gate-sim （网表仿真）。不要用延迟。不需要从DC输出SDF，因为那个根本不准，而且它也无法保证没有hold违反 Q1.3 如何让DC自动插入clock
2012-08-31 15:57:28
4914
转载 时序约束，STA
(1) clockQ1.1什么是同步时钟？时钟频率是整倍数，并且相互之间的相位是固定而且相差可预知的，才可以称得上是同步时钟。其他的都算异步时钟。比如，5M，10M是同步2M，3M一般算异步一个时钟，输出到另一个芯片中，转一圈后，以同样的频率返回到自己的芯片，因为无法确定时钟在另一个芯片里面的latency，所以输出的时钟与输入的时钟算异步一个时钟进到2个PLL，就算那
2012-08-31 15:55:53
12179
原创 数字后端面试问题
1.1 EETOP版主面试问题001）Why power stripes routed in the top metal layers?为什么电源走线选用最上面的金属层？因为顶层金属通常比较厚，可以通过较大的电流1.高层更适合globalrouting.低层使用率比较高，用来做power的话会占用一些有用的资源，比如std cell 通常是m1 Pin 。2. EM能力
2012-08-31 15:51:59
75338
4
原创 不同时钟域的时序问题
1.慢时钟域到快时钟域检查建立时间和保持时间的检查：Here are the clock definitions for our example.create_clock -name CLKM \-period 20 -waveform {0 10} [get_ports CLKM]create_clock -name CLKP \-period 5 -waveform
2012-08-31 14:36:24
11938
原创 timing verification----recovery timing check
A recovery timing check ensures that there is a minimum amount of time between the asynchronous signal becoming inactive and the next active clock edge. In other words, this check ensures that after
2012-08-31 10:17:02
2892
原创 timing verification--Removal Timing Check
A removal timing check ensures that there is adequate time between an active clock edge and the release of an asynchronous control signal. The check ensures that the active clock edge has no effect be
2012-08-31 09:53:11
1836
原创 timing verification--Half-Cycle Paths
If a design has both negative-edge triggered flip-flops (active clock edge is falling edge) and positive-edge triggered flip-flops (active clock edge is rising edge), it is likely that half-cycle pa
2012-08-31 09:27:33
1880
原创 timing verification---虚假路径
It is possible that certain timing paths are not real (or not possible) in the actual functional operation of the design. Such paths can be turned off during STA by setting these as false paths. A fal
2012-08-31 09:10:48
1876
原创 timing check---多周期路径
In some cases, the combinational data path between two flip-flops can take more than one clock cycle to propagate through the logic. In such cases, the combinational path is declared as a multicycle
2012-08-30 18:25:04
5090
原创 timing verification---hold time check
A hold timing check ensures that a flip-flop output value that is changing does not pass through to a capture flip-flop and overwrite its output before the flip-flop has had a chance to capture its or
2012-08-30 15:43:43
4323
原创 timing verification---setup timing check
The setup check can be mathematically expressed as:Tlaunch + Tck2q + Tdp where Tlaunch is the delay of the clock tree of the launch flip-flop UFF0, Tdp is the delay of the combinational logic data
2012-08-30 14:20:12
4977
原创 设置静态时序分析环境
setting up clocks, specifying IO timing characteristics, and specifying false paths and multicycle paths1.Specifying Clockscreate_clockset_clock_transition：This specification applies only fo
2012-08-28 22:08:02
11462
原创 Timing Modeling--时序模型
The cell timing models are intended to provide accurate timing for various instances of the cell in the design environment. The timing models are normally obtained from detailed circuit simulations
2012-08-28 16:19:21
5146
原创 Operating Conditions-工作条件
Static timing analysis is typically performed at a specific operating condition1.Anoperating conditionis defined as a combination of Process, Voltage and Temperature (PVT). Cell delays and interconn
2012-08-28 14:20:44
2359
原创 Clock Domains--时钟域
A clock typically feeds a number of flip-flops. The set of flip-flops being fed by one clock is called itsclock domain. In a typical design, there may be more than one clock domain.A question
2012-08-28 11:42:59
2518
原创 Min and Max Timing Paths--时序路径
The total delay for the logic to propagate through a logic path is referred to as thepath delay. This corresponds to the sum of the delays through the various logic cells and nets along the path. In
2012-08-28 11:06:47
1729
原创 Timing Arcs and Unateness
Every cell has multipletiming arcs. For example, a combinational logic cell, such as and, or, nand, nor, adder cell, has timing arcs from each input to each output of the cell. Sequential cells such
2012-08-28 09:09:26
3855
原创 Slew of a Waveform
A slew rate is defined as a rate of change. In static timing analysis, the rising or falling waveforms are measured in terms of whether the transition is slow or fast. The slew is typically measured i
2012-08-27 22:18:23
1053
原创 Skew between Signals
Skew is the difference in timing between two or more signals, maybe data,clock or both. For example, if a clock tree has 500 end points and has a skew of 50ps, it means that the difference in latenc
2012-08-27 22:07:36
1205
转载 验证方法学的历史及比较
2000年, Verisity Design（现在的Cadence Design System公司）引进了Verification Advisor（vAdvisor）采用了e语言，包含了激励的产生，自动比对的策略，覆盖率模型。e语言是面向对象语言，这是业界开始使用面向对象语言进行测试平台的建立。2002年，Verisity公司公布了第一个验证库——e可重用方法学（eRM）。 2003年
2012-08-07 09:42:13
12018
高质量程序设计 高质量程序设计
2010-04-21
空空如也
TA创建的收藏夹 TA关注的收藏夹
TA关注的人