timing check---多周期路径

最新推荐文章于 2024-02-05 14:54:16 发布

mikiah

最新推荐文章于 2024-02-05 14:54:16 发布

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分类专栏： STA

本文链接：https://blog.csdn.net/mikiah/article/details/7925931

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本文介绍了在组合数据路径需要多个时钟周期才能通过逻辑门的情况，这种路径被称为多周期路径。设置多周期路径可以调整时序分析，确保数据在指定的时钟周期后被捕获。在保持时序检查中，通常希望保持检查保持单周期设置时的状态，为此需要指定多周期保持约束。例如，当设置了一个3周期的设置多周期路径，应配合一个2周期的保持多周期路径，以便将保持检查边缘移回到发射边缘。同时，跨时钟域的多周期路径也需要相应的设置和保持约束。

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In some cases, the combinational data path between two flip-flops can take more than one clock cycle to propagate through the logic. In such cases, the combinational path is declared as a multicycle path. Even though the data is being captured by the capture flip-flop on every clock edge, we direct STA that the relevant capture edge occurs after the specified number of clock cycles.

create_clock -name CLKM -period 10 [get_ports CLKM]
set_multicycle_path 3 -setup \
-from [get_pins UFF0/Q] \
-to [get_pins UFF1/D]