More Verilog Features

最新推荐文章于 2024-07-17 18:38:35 发布

且听风吟567

最新推荐文章于 2024-07-17 18:38:35 发布

阅读量216

点赞数 3

分类专栏： HDLBits 文章标签：笔记 fpga开发

本文链接：https://blog.csdn.net/pmlcreating/article/details/137167195

版权

HDLBits 专栏收录该内容

32 篇文章 0 订阅

订阅专栏

1.Conditional ternary operator

module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);//

    // assign intermediate_result1 = compare? true: false;
    reg state;
    reg [7:0] min1;
    reg [7:0] min2;
    always@(*)
        begin
            if(a>b)
                min1=b;
            else min1=a;
            if(c>d)
                min2=d;
            else min2=c;
            if(min2>min1)
                min=min1;
            else min=min2;
        end

endmodule

2.Reduction operators

module top_module (
    input [7:0] in,
    output parity); 
    
    assign parity=^in[7:0];

endmodule

3.Reduction Even wider gates

module top_module( 
    input [99:0] in,
    output out_and,
    output out_or,
    output out_xor 
);
    
    assign out_and = &in[99:0];
    assign out_or = |in[99:0];
    assign out_xor = ^in[99:0];

endmodule

4.Combinational for loop Vector reversal 2

module top_module( 
    input [99:0] in,
    output [99:0] out
);

    integer i;
    always@(*)
        begin
            for(i=0;i<100;i++)
                begin
                     out[i] =in[99-i];
                end
        end
endmodule

5.Combinational for loop 255-bit

module top_module( 
    input [254:0] in,
    output [7:0] out );
    
    
    integer i;
    always@(*)
        begin
            out = 8'd0;
            for(i=0;i<255;i++)
                begin
                    if(in[i]==1)
                        out=out+8'd1;              
                end        
        end
endmodule

6.Generate for loop 100bit binary adder 2

module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );
    
  integer i;
    always @(*)
        begin
            for(i=0;i<100;i++)
                begin
                if(i==0)
            		{cout[0],sum[0]}=a[0]+b[0]+cin;
                    else {cout[i],sum[i]}=a[i]+b[i]+cout[i-1];
                end
        end
endmodule

7.Generate for loop digit BCD adder

module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );
    reg [400:0] sum1;
    
   genvar i;
    wire [99:0] cout_temp;
    
    generate
        for(i=0;i<100;i++)
            
            begin: bcd_fadd
                if(i==0)
                    bcd_fadd bcd_inst(a[3:0],b[3:0],cin,cout_temp[0],sum[3:0]);
                else
                    bcd_fadd bcd_inst(a[4*i+3:4*i],b[4*i+3:4*i],cout_temp[i-1],cout_temp[i],sum[4*i+3:4*i]);
            end
        assign cout=cout_temp[99];
    endgenerate

endmodule