verilog无法实现双边沿触发只能单边沿触发,所以我们要实现双边沿触发的方法如下:
reg temp,temp1;
always @(posedge clk) begin
temp <= d ^ temp1;
end
always @(negedge clk) begin
temp1 <= d ^ temp;
end
assign q = temp ^ temp1;
原理如下:
// After posedge clk, temp = d ^ temp1. Thus q = d ^ temp1 ^ temp1 = d.
// After negedge clk, temp1 = d ^ temp . Thus q = d ^ temp ^ temp = d.