verilog边沿触发究竟是怎么搞的？

    always @(posedge clk)
    result<=a1+a2;
    always @(posedge clk)
    a1<=a1+1;        
    always @(posedge clk)
    a2<=a2+1;  
    

在时钟上升沿处理：右边数据在上升沿之前的大小值。

卡诺图化简是消除相同的，如果圈1的话是最小项之和，圈0的话是圈1的反函数，需要再加一次非。

边沿检测

always@(*)
    begin
    pulse_r1 <= pulse;
    pulse_r2 <= pulse_r1;
    end
assign pos_edge = (pulse_r1 && ~pulse_r2) ?1:0;
assign neg_edge = (~pulse_r1 && pulse_r2) ?1:0; 

只执行一次（来自百度知道）

assign Flag = (Count <= xxxx) ? 1 : 0 ; 
always @ (posedge Clk or negedge RSTn) 
begin
    if(~RSTn) 
        Count <= 0 ;
    else if(Count <= xxxxx) 
        Count <= Count + 1 ;
    else
        Count <= Count ;
end 
 always @ (posedge Clk or negedge RSTn) 
begin
    if(~RSTn) 
        /*code*/
    else if(Flag == 1) 
        /*code*/
end