verilog/dc/fm中的undriven问题

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一、什么是undriven？

The object is undriven if no real driver is connected to the object.

由上图可知，undriven input pins和undriven output ports会比较严重，因为这两种情况不定态X会传递最终导致后面的逻辑出错。
undriven input pin: input pins that do not have a connected net, or have a connected net but do not have a driving pin.
undriven output port: output ports that do not have a connected net, or have a connected net but do not have a driving pin.

1. verilog中的undriven问题

代码如下（示例）：

module half_adder(
   input                A   , 
   input                B   , 
 
   output	wire        S   , 
   output   wire        C    
);

assign S = A ^ B; 
assign C = A & B; 
endmodule

module full_adder(
   input                A   ,
   input                B   ,
   input                Ci  , 
   input                Ui  , //undriven input port
   
   output	wire        S   ,
   output   wire        Co 	,
   output   wire        Uo   //undriven output port
);
    wire [1:0] s, c;
    wire Ui; 
    wire Uo; 
    half_adder m1 (
        .A(A),
        .B(B),
        .S(s[0]),
        .C(c[0]));
    
    half_adder m2 (