解决vivado抓取ila信号名错乱问题

        摘要：vivado ila 信号名错乱

1、写在前面

        在Xilinx FPGA开发当中，使用vivado工具的ila进行信号的抓取调试是非常常见的使用场景。使用ila大致有两种方式，一种是直接例化ila IP核，另一种是通过添加属性的方式（*mark_debug = "true", dont_touch = "true"*）。

        然后，有时候你会发现不管是例化ila IP核还是直接对要抓取的信号添加上述属性再set up as debug，都有出现信号名错乱的问题。明明是一个信号，即使设置了(*dont_touch = "true"*)属性依旧被拆分成好几部分，在设置触发的或者观察信号的时候就很麻烦。

2、错乱原因

        vivado综合生成网表有自己的一套规则，在综合过程中会进行信号的优化。这个时候呈现在ila端口的就是优化后的信号，经过测试发现单纯的添加属性实际上并没有多大作用。那么这个信号错乱问题该怎么解决呢？

3、解决办法

        解决办法其实也很简单，对要观察的信号打一拍再进入ila即可。有的时候信号是从IP核出来的，不知道其所在时钟域。这个时候可以对这个信号设置mark_debug属性，综合之后通过set up as debug基本上可以找到该信号所在时钟域，记下来即可。如果想在同一个ila下观察，那就要做好跨时钟域处理并添加好相关约束。

4、示例说明

        例化ila IP核方式示例

    (*dont_touch = "true"*)reg                                  dbg_tx_swrite_start;
    (*dont_touch = "true"*)reg                                  dbg_tx_swrite_end;
    (*dont_touch = "true"*)reg   [33:0]                         dbg_tx_swrite_addr;
    (*dont_touch = "true"*)reg   [7:0]                          dbg_tx_swrite_byte_size;
    (*dont_touch = "true"*)reg   [63:0]                         dbg_tx_swrite_data;
    (*dont_touch = "true"*)reg                                  dbg_tx_swrite_data_valid;
    (*dont_touch = "true"*)reg                                  dbg_tx_swrite_data_ready;
    (*dont_touch = "true"*)reg                                  dbg_tx_doorbell_start;
    (*dont_touch = "true"*)reg                                  dbg_tx_doorbell_end;
    (*dont_touch = "true"*)reg   [7:0]                          dbg_tx_doorbell_srctid;
    (*dont_touch = "true"*)reg   [15:0]                         dbg_tx_doorbell_msg;

    always @(posedge user_clk ) begin
        dbg_tx_swrite_start <= #simTdly tx_swrite_start;
        dbg_tx_swrite_end <= #simTdly tx_swrite_end;
        dbg_tx_swrite_addr <= #simTdly tx_swrite_addr;
        dbg_tx_swrite_byte_size <= #simTdly tx_swrite_byte_size;
        dbg_tx_swrite_data <= #simTdly tx_swrite_data;
        dbg_tx_swrite_data_valid <= #simTdly tx_swrite_data_valid;
        dbg_tx_swrite_data_ready <= #simTdly tx_swrite_data_ready;
        dbg_tx_doorbell_start <= #simTdly tx_doorbell_start;
        dbg_tx_doorbell_end <= #simTdly tx_doorbell_end;
        dbg_tx_doorbell_srctid <= #simTdly tx_doorbell_srctid;
        dbg_tx_doorbell_msg <= #simTdly tx_doorbell_msg;
    end

    wire  [255:0] probe0;

    assign probe0 = {
        108'd0,
        dbg_tx_swrite_start,
        dbg_tx_swrite_end,
        dbg_tx_swrite_addr,
        dbg_tx_swrite_byte_size,
        dbg_tx_swrite_data,
        dbg_tx_swrite_data_valid,
        dbg_tx_swrite_data_ready,
        dbg_tx_doorbell_start,
        dbg_tx_doorbell_end,
        dbg_tx_doorbell_srctid,
        dbg_tx_doorbell_msg
    };

    ila_2 ila_srio_0_tx (
        .clk    (user_clk), //
        .probe0 (probe0  )  //
    );

        mark_debug方式示例

    // debug
    (*mark_debug = "true", dont_touch = "true"*)reg   [7:0]                                 dbg_tx_data;
    (*mark_debug = "true", dont_touch = "true"*)reg                                         dbg_tx_plus;
    (*mark_debug = "true", dont_touch = "true"*)reg                                         dbg_tx_busy;
    (*mark_debug = "true", dont_touch = "true"*)reg                                         dbg_tx_done;
    (*mark_debug = "true", dont_touch = "true"*)reg                                         dbg_tx;

    (*mark_debug = "true", dont_touch = "true"*)reg                                         dbg_tx_flag;
    (*mark_debug = "true", dont_touch = "true"*)reg   [15:0]                                dbg_cnt_bund;
    (*mark_debug = "true", dont_touch = "true"*)reg                                         dbg_bit_flag;
    (*mark_debug = "true", dont_touch = "true"*)reg   [3:0]                                 dbg_cnt_bit;
    (*mark_debug = "true", dont_touch = "true"*)reg   [8:0]                                 dbg_tx_data_reg;

    always @(posedge clk ) begin
        dbg_tx_data <= #simTdly tx_data;
        dbg_tx_plus <= #simTdly tx_plus;
        dbg_tx_busy <= #simTdly tx_busy;
        dbg_tx_done <= #simTdly tx_done;
        dbg_tx <= #simTdly tx;

        dbg_tx_flag <= #simTdly tx_flag;
        dbg_cnt_bund <= #simTdly cnt_bund;
        dbg_bit_flag <= #simTdly bit_flag;
        dbg_cnt_bit <= #simTdly cnt_bit;
        dbg_tx_data_reg <= #simTdly tx_data_reg;
    end