FPGA学习-Verilog实现LED电平转换
作者:小铁匠
8/2/2019 8:38:30 AM
运行代码如下:
module test(clk,rst_n,led);
input clk ;
input rst_n ;
output reg led ;
always @ ( posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
led<=0;
end
else
begin
led<=~led;
end
end
endmodule
仿真代码如下:
module test_tb();
reg clk;
reg rst_n;
wire led;
test i1 (
.clk(clk),
.led(led),
.rst_n(rst_n)
);
initial
begin
$display("Running testbench");
clk=0;
rst_n=0;
end
always #1000 rst_n=~rst_n;
always #10 clk=~clk;
endmodule
always #10 clk=~clk;
endmodule
仿真时序图如下: