Verilog编写通用模块

:移位寄存器, ALU, 多路选择器,二进制乘法器,模N计数器,约翰逊计数器,参数化比较器,约翰逊译码器

移位寄存器:

module unishiftregister(clk,reset,leftin,rightin,sel,loaddta,Q);
parameter Nbits = 4:

input clk,reset,leftin,rightin;
input [1:0] sel;
input [Nbits-1:0] loaddta;
output [Nbits-1:0] Q;
reg [Nbits-1:0] Q;

always @(posedge clk)
	if(reset==1)
		Q<=0;
	else 
		case(sel)
			2'b00: ;
			2'b01:Q<={Q[Nbits-2:0],leftin};
			2'b10:Q<={rightin,Q[Nbits-1:1]};
			2'b11:Q<=loaddta;
		endcase
endmodule

简单ALU(使用assign):

module ArithLogicUnit(A,B,OpCode,DataZ,CompZ);

parameter Nbits = 2;
input [Nbits-1:0] A,B;
input [1:0] Opcode;
output [Nbits-1:0] DataZ;
output CompZ;

parameter AND_OP=0,NAND_OP=1,GT_OP=2,XOR_OP=3;

assign DataZ = (Opcode == AND_OP)?  A & B:
			   (Opcode == NAND_OP)? ~(A&B):
			   (Opcode == XOR_OP)?  A`B:
			   'bx;

assign CompZ = (OpC