用Verilog HDL实现4位超前进位加法器

mccree618

已于 2022-06-12 20:53:15 修改

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分类专栏： Verilog 文章标签：超前进位加法器逻辑表达 Verilog 全加器数字逻辑

于 2022-06-12 20:50:25 首次发布

本文链接：https://blog.csdn.net/mccree618/article/details/125246682

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4位超前进位加法器的逻辑表达

4位全加器的逻辑表达如下

$C_{i+1}=A_{i}B_{i}+A_{i}C_{i}+B_{i}C_{i}\qquad(1)$

$S_{i}=A_{i}\oplus B_{i} \oplus C_{i}\qquad(2)$

按照异或如下性质

$M\oplus N=(M_{i}N_{i})\oplus (M+N)\qquad(3)$

将其代入(1)与(2)，有

$C_{i+1}=A_{i}B_{i}+(A_{i}+B_{i})C_{i}\qquad(4)$

$S_{i}=(A_{i}B_{i})\oplus (A_{i}+B_{i})\oplus C_{i}\qquad(5)$

引入辅助标记量 P(表示 A或B)，G(表示 A与B)，即

$P_{i}=A_{i}+B_{i}$

$G_{i}=A_{i}B_{i}$

并代入(4)与(5)，得

$C_{i+1}=G_{i}+P_{i}C_{i}\qquad(6)$

$S_{i}=G_{i}\oplus P_{i}\oplus C_{i}\qquad(7)$

至此，4位超前加法器的逻辑表达式已得到，如式(6)与(7)所示，展开后有

$C_{1}=G_{0}+P_{0}C_{0}$

$C_{2}=G_{1}+P_{1}(G_{0}+P_{0}C_{0})=G_{1}+P_{1}G_{0}+P_{1}P_{0}C_{0}$

$C_{3}=G_{2}+P_{2}(G_{1}+P_{1}(G_{0}+P_{0}C_{0}))=G_{2}+P_{2}G_{1}+P_{2}P_{1}G_{0}+P_{2}P_{1}P_{0}C_{0}$

$C_{4}=G_{3}+P_{3}G_{2}+P_{3}P_{2}G_{1}+P_{3}P_{2}P_{1}G_{0}+P_{3}P_{2}P_{1}P_{0}C_{0}$

$S_{0}=G_{0}\oplus P_{0}\oplus C_{0}$

$S_{1}=G_{1}\oplus P_{1}\oplus (G_{0}+P_{0}C_{0})$

$S_{2}=G_{2}\oplus P_{2}\oplus (G_{1}+P_{1}(G_{0}+P_{0}C_{0}))$

$S_{3}=G_{3}\oplus P_{3}\oplus (G_{2}+P_{2}(G_{1}+P_{1}(G_{0}+P_{0}C_{0})))$

Verilog 实现

1、采用数据流建模

module four_bits_fast_adder();
input [3:0] a,b;
input c_in;
output [3:0] sum;
output c_out;
wire[4:0] g,p,c;

assign c[0] = c_in;
assign g = a & b;
assign p = a | b;
assign c[1] = g[0]|(p[0]&c[0]);
assign c[2] = g[1]|(p[1]&g[0])|(p[1]&p[0]&c[0]);
assign c[3] = g[2]|(p[2]&g[1])|(p[2]&p[1]&g[0])|(p[2]&p[1]&p[0]&c[0]);
assign c[4] = g[3]|(p[3]&g[2])|(p[3]&p[2]&g[1])|(p[3]&p[2]&p[1]&g[0])|(p[3]&p[2]&p[1]&p[0]&c[0]);
assign sum = g^p^c[3:0];
assign c_out = c[4];
endmodule