//流水线之3个乘法器实现S=abc*d
module cy4(input[3:0] a,b,c,d,
input vld_in,//输入有效指示信号
input clk,rst_n,
output reg[15:0] dout,
output reg vld_out//输出有效指示信号
);
reg vld_in_ff0;//中间缓存寄存器
always @(posedge clk or negedge rst_n)
if(rst_n==1'b0) dout <= 0;
else dout <= a * b * c * d;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
vld_out <= 0;
vld_in_ff0 <= 0;
end
else begin
vld_in_ff0 <= vld_in;
vld_out <= vld_in_ff0;
end
end
endmodule