HDLBits Bugs case

最新推荐文章于 2024-09-12 17:09:49 发布

闪光的正幸

最新推荐文章于 2024-09-12 17:09:49 发布

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分类专栏： FPGA HDLBits刷题文章标签： fpga开发

本文链接：https://blog.csdn.net/qq_43406377/article/details/129259599

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1、注意细心，8位并且是十六进制。运行一下看看波形就行了

2、修改后的代码如下

module top_module (
    input [7:0] code,
    output reg [3:0] out,
    output reg valid );//

    always @(*)begin
        case (code)
            8'h45: out = 0;
            8'h16: out = 1;
            8'h1e: out = 2;
            8'h26: out = 3;
            8'h25: out = 4;
            8'h2e: out = 5;
            8'h36: out = 6;
            8'h3d: out = 7;
            8'h3e: out = 8;
            8'h46: out = 9;
            default: out = 0;
        endcase
    end
     always @(*)begin
        case (code)
            8'h45: valid = 1;
            8'h16: valid = 1;
            8'h1e: valid = 1;
            8'h26: valid = 1;
            8'h25: valid = 1;
            8'h2e: valid = 1;
            8'h36: valid = 1;
            8'h3d: valid = 1;
            8'h3e: valid = 1;
            8'h46: valid = 1;
            default: valid = 0;
        endcase
    end
endmodule