HDLBits verlog刷题-Finding bugs in code-05_Bugs case

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HDLBITs_reading simulations

题目描述-Bugs case

This combinational circuit is supposed to recognize 8-bit keyboard scancodes for keys 0 through 9. It should indicate whether one of the 10 cases were recognized (valid), and if so, which key was detected. Fix the bug(s).
即
8位的键盘， 用唯一的8位数据 分别代表密码0–9
输入8位code，有对应上的0–9被输出（key was detected） vilid=1
注意
out 3和9的code 故意给错，服了

Module Declaration
module top_module (
    input [7:0] code,
    output reg [3:0] out,
    output reg valid=1 );

参考资料

代码部分

/**************分析***************************
8位的键盘   用唯一的8位数据    分别代表0--9
valid  输入code,有对应的0--9被输出（key was detected）   vilid=1

********************************************/
module top_module (
    input [7:0] code,
    output reg [3:0] out,
    output reg valid=1 );//
/***********有bug****************************
     always @(*)
        case (code)
            8'h45: out = 0;
            8'h16: out = 1;
            8'h1e: out = 2;
            8'h26: out = 3;//改h
            8'h25: out = 4;
            8'h2e: out = 5;
            8'h36: out = 6;
            8'h3d: out = 7;
            8'h3e: out = 8;
            8'h46: out = 9;//位宽错误，服了
            default: valid = 0;
        endcase
************************************************/
/**************正确实现*************************/
  always @(*)
        case (code)
            8'h45: out = 0;
            8'h16: out = 1;
            8'h1e: out = 2;
            8'd26: out = 3;
            8'h25: out = 4;
            8'h2e: out = 5;
            8'h36: out = 6;
            8'h3d: out = 7;
            8'h3e: out = 8;
            6'h46: out = 9;
            default: out = 0;//如果code为其它数   out=0
        endcase   
    //组合逻辑  out为0且输入的code不代表密码0时  vilid=0
    //否则key was detected    vilid=1
    always@(*)  
        valid=(out==4'd0 && code!=8'h45)?0:1;
endmodule