GTXE2_COMMON 原语

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最新推荐文章于 2024-04-28 10:27:47 发布

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分类专栏： GTX 高速接口 FPGA 文章标签：学习

本文链接：https://blog.csdn.net/qq_43807800/article/details/135895486

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1、GTX Transceiver Quad Configuration

GTX一个Quad包含一个gtx_common、四个GTXE2 channels，具体可以查看官方手册ug476-25页。

2、参考时钟选择

参考ug476-36页

对于一个Quad中，参考时钟由6个时钟的可能：

两个时钟来自管脚，GTREFCLK0 和 GTREFCLK1
两个时钟来自这个Quad的上方的时钟，GTSOUTHREFCLK0 和 GTSOUTHREFCLK1
两个时钟来自这个Quad的下方的时钟，GTNORTHREFCLK0 和 GTNORTHREFCLK1

针对QPLL时钟的选择，参考时钟的选择如下图所示，具体可以查看官方手册ug476-35页。

针对于选择哪个一个参考时钟是根据QPLLREFCLKSEL[2:0]的值确定。具体可以查看官方手册ug476-40页。

QPLL和CPLL的区别，在于两者支持的线速率不同，对于CPLL来说，支持的线速率位1.6GHz到3.3GHZ之间，而对于QPLL来说，GTX支持的线速率分两档，Lower Baud支持5.93GHz~8.0GHz，Upper Baud支持9.8GHz~12.5GHz，对于GTH则不分档位，支持的线速率为8.0GHz~13.1GHz

3、gtx_common原语

具体原语如下代码所示。

///
//   ____  ____ 
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version : 3.6
//  \   \         Application : 7 Series FPGAs Transceivers Wizard
//  /   /         Filename : gtx_coregen_fc_common.v
// /___/   /\     
// \   \  /  \ 
//  \___\/\___\
//
//
// Module gtx_coregen_fc_common 
// Generated by Xilinx 7 Series FPGAs Transceivers Wizard
// 
// 
// (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
// 
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
// 
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
// 
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
// 
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES. 


`default_nettype wire

`timescale 1ns / 1ps
`define DLY #1
//***************************** Entity Declaration ****************************
module gtx_coregen_fc_common #
(
    // Simulation attributes
    parameter   WRAPPER_SIM_GTRESET_SPEEDUP    =   "TRUE",     // Set to "true" to speed up sim reset
    parameter   SIM_QPLLREFCLK_SEL             =   3'b001     
)
(
    input   [2:0]   QPLLREFCLKSEL_IN,     	//参考时钟的选择端口
    input           GTREFCLK0_IN,			//管脚输入的参考时钟0
    input           GTREFCLK1_IN,			//管脚输入的参考时钟1
    output          QPLLLOCK_OUT,
    input           QPLLLOCKDETCLK_IN,
    output          QPLLOUTCLK_OUT,
    output          QPLLOUTREFCLK_OUT,
    output          QPLLREFCLKLOST_OUT,   
    input           QPLLRESET_IN
);

wire 				GTGREFCLK_IN		;
wire 				GTNORTHREFCLK0_IN 	;
wire 				GTNORTHREFCLK1_IN 	;
wire 				GTREFCLK0_IN		;
wire 				GTREFCLK1_IN		;
wire 				GTSOUTHREFCLK0_IN	;
wire 				GTSOUTHREFCLK1_IN	;


//根据自己的设计选择对应的参考时钟
assign {GTGREFCLK_IN,GTNORTHREFCLK0_IN,GTNORTHREFCLK1_IN,GTREFCLK0_IN,
		GTREFCLK1_IN,GTSOUTHREFCLK0_IN,GTSOUTHREFCLK1_IN} = QPLLREFCLKSEL_IN == 3'b001	? {3'd0,GTREFCLK0_IN,3'd0} :
															QPLLREFCLKSEL_IN == 3'b010	? {4'd0,GTREFCLK0_IN,2'd0} :																									
															QPLLREFCLKSEL_IN == 3'b011	? {1'd0,GTREFCLK0_IN,5'd0} :																									
															QPLLREFCLKSEL_IN == 3'b100	? {2'd0,GTREFCLK0_IN,4'd0} :																									
															QPLLREFCLKSEL_IN == 3'b101	? {5'd0,GTREFCLK0_IN,1'd0} :																									
															QPLLREFCLKSEL_IN == 3'b110	? {6'd0,GTREFCLK0_IN} 	   :																									
															QPLLREFCLKSEL_IN == 3'b111	? {GTREFCLK0_IN,6'd0}      : {3'd0,GTREFCLK0_IN,3'd0};																									


//***************************** Parameter Declarations ************************
    localparam QPLL_FBDIV_TOP =  16;

    localparam QPLL_FBDIV_IN  =  (QPLL_FBDIV_TOP == 16)  ? 10'b0000100000 : 
				(QPLL_FBDIV_TOP == 20)  ? 10'b0000110000 :
				(QPLL_FBDIV_TOP == 32)  ? 10'b0001100000 :
				(QPLL_FBDIV_TOP == 40)  ? 10'b0010000000 :
				(QPLL_FBDIV_TOP == 64)  ? 10'b0011100000 :
				(QPLL_FBDIV_TOP == 66)  ? 10'b0101000000 :
				(QPLL_FBDIV_TOP == 80)  ? 10'b0100100000 :
				(QPLL_FBDIV_TOP == 100) ? 10'b0101110000 : 10'b0000000000;

   localparam QPLL_FBDIV_RATIO = (QPLL_FBDIV_TOP == 16)  ? 1'b1 : 
				(QPLL_FBDIV_TOP == 20)  ? 1'b1 :
				(QPLL_FBDIV_TOP == 32)  ? 1'b1 :
				(QPLL_FBDIV_TOP == 40)  ? 1'b1 :
				(QPLL_FBDIV_TOP == 64)  ? 1'b1 :
				(QPLL_FBDIV_TOP == 66)  ? 1'b0 :
				(QPLL_FBDIV_TOP == 80)  ? 1'b1 :
				(QPLL_FBDIV_TOP == 100) ? 1'b1 : 1'b1;

    // ground and vcc signals
wire            tied_to_ground_i;
wire    [63:0]  tied_to_ground_vec_i;
wire            tied_to_vcc_i;
wire    [63:0]  tied_to_vcc_vec_i;

    assign tied_to_ground_i             = 1'b0;
    assign tied_to_ground_vec_i         = 64'h0000000000000000;
    assign tied_to_vcc_i                = 1'b1;
    assign tied_to_vcc_vec_i            = 64'hffffffffffffffff;

    //_________________________________________________________________________
    //_________________________________________________________________________
    //_________________________GTXE2_COMMON____________________________________

    GTXE2_COMMON #
    (
            // Simulation attributes
            .SIM_RESET_SPEEDUP   (WRAPPER_SIM_GTRESET_SPEEDUP),
            .SIM_QPLLREFCLK_SEL  (SIM_QPLLREFCLK_SEL),
            .SIM_VERSION         ("4.0"),


           //----------------COMMON BLOCK Attributes---------------
            .BIAS_CFG                               (64'h0000040000001000),
            .COMMON_CFG                             (32'h00000000),
            .QPLL_CFG                               (27'h06801C1),
            .QPLL_CLKOUT_CFG                        (4'b0000),
            .QPLL_COARSE_FREQ_OVRD                  (6'b010000),
            .QPLL_COARSE_FREQ_OVRD_EN               (1'b0),
            .QPLL_CP                                (10'b0000011111),
            .QPLL_CP_MONITOR_EN                     (1'b0),
            .QPLL_DMONITOR_SEL                      (1'b0),
            .QPLL_FBDIV                             (QPLL_FBDIV_IN),
            .QPLL_FBDIV_MONITOR_EN                  (1'b0),
            .QPLL_FBDIV_RATIO                       (QPLL_FBDIV_RATIO),
            .QPLL_INIT_CFG                          (24'h000006),
            .QPLL_LOCK_CFG                          (16'h21E8),
            .QPLL_LPF                               (4'b1111),
            .QPLL_REFCLK_DIV                        (1)

    )
    gtxe2_common_i
    (
        //----------- Common Block  - Dynamic Reconfiguration Port (DRP) -----------
        .DRPADDR                        (tied_to_ground_vec_i[7:0]),
        .DRPCLK                         (tied_to_ground_i),
        .DRPDI                          (tied_to_ground_vec_i[15:0]),
        .DRPDO                          (),
        .DRPEN                          (tied_to_ground_i),
        .DRPRDY                         (),
        .DRPWE                          (tied_to_ground_i),
        //-------------------- Common Block  - Ref Clock Ports ---------------------
        .GTGREFCLK                      (GTGREFCLK_IN		),
        .GTNORTHREFCLK0                 (GTNORTHREFCLK0_IN 	),
        .GTNORTHREFCLK1                 (GTNORTHREFCLK1_IN 	),
        .GTREFCLK0                      (GTREFCLK0_IN		),
        .GTREFCLK1                      (GTREFCLK1_IN		),
        .GTSOUTHREFCLK0                 (GTSOUTHREFCLK0_IN	),
        .GTSOUTHREFCLK1                 (GTSOUTHREFCLK1_IN	),
        //----------------------- Common Block -  QPLL Ports -----------------------
        .QPLLDMONITOR                   (),
        //--------------------- Common Block - Clocking Ports ----------------------
        .QPLLOUTCLK                     (QPLLOUTCLK_OUT),
        .QPLLOUTREFCLK                  (QPLLOUTREFCLK_OUT),
        .REFCLKOUTMONITOR               (),
        //----------------------- Common Block - QPLL Ports ------------------------
        .QPLLFBCLKLOST                  (),
        .QPLLLOCK                       (QPLLLOCK_OUT),
        .QPLLLOCKDETCLK                 (QPLLLOCKDETCLK_IN),
        .QPLLLOCKEN                     (tied_to_vcc_i),
        .QPLLOUTRESET                   (tied_to_ground_i),
        .QPLLPD                         (tied_to_vcc_i),
        .QPLLREFCLKLOST                 (QPLLREFCLKLOST_OUT),
        .QPLLREFCLKSEL                  (QPLLREFCLKSEL_IN),
        .QPLLRESET                      (QPLLRESET_IN),
        .QPLLRSVD1                      (16'b0000000000000000),
        .QPLLRSVD2                      (5'b11111),
        //------------------------------- QPLL Ports -------------------------------
        .BGBYPASSB                      (tied_to_vcc_i),
        .BGMONITORENB                   (tied_to_vcc_i),
        .BGPDB                          (tied_to_vcc_i),
        .BGRCALOVRD                     (5'b11111),
        .PMARSVD                        (8'b00000000),
        .RCALENB                        (tied_to_vcc_i)

    );
endmodule

根据模块外部输入的QPLLREFCLKSEL_IN值选择对饮哪一个参考时钟。