xilinx FPGA 开方（cordic）ip核的使用（VIVADO&VHDL）

一、建立ip核

 根据自己的要求自行更改：

选择开发模式，然后模式可以选择最优或者最大，数据格式可以选择无符号整数或者无符号分数，然后再选择输入位宽，以及就散模式，向下取整或者四舍五入等等。

二、建VHDL程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity kaifang0 is
PORT (
    clk : IN STD_LOGIC;
    s_axis_cartesian_tvalid : IN STD_LOGIC;
    s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
    m_axis_dout_tvalid : OUT STD_LOGIC;
    m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
  );
end kaifang0;

architecture Behavioral of kaifang0 is

COMPONENT cordic_0
  PORT (
    aclk : IN STD_LOGIC;
    s_axis_cartesian_tvalid : IN STD_LOGIC;
    s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
    m_axis_dout_tvalid : OUT STD_LOGIC;
    m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
  );
END COMPONENT;

begin

kaif0 : cordic_0
  PORT MAP (
    aclk => clk,
    s_axis_cartesian_tvalid => s_axis_cartesian_tvalid,
    s_axis_cartesian_tdata => s_axis_cartesian_tdata,
    m_axis_dout_tvalid => m_axis_dout_tvalid,
    m_axis_dout_tdata => m_axis_dout_tdata
  );
  
end Behavioral;

三、RTL图：

 

四、仿真程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity kaifang0_tb is
--  Port ( );
end kaifang0_tb;

architecture Behavioral of kaifang0_tb is

COMPONENT kaifang0
  PORT (
    clk : IN STD_LOGIC;
    s_axis_cartesian_tvalid : IN STD_LOGIC;
    s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
    m_axis_dout_tvalid : OUT STD_LOGIC;
    m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
  );
END COMPONENT;

signal clk :  STD_LOGIC;
signal    s_axis_cartesian_tvalid :  STD_LOGIC;
signal    s_axis_cartesian_tdata :  STD_LOGIC_VECTOR(23 DOWNTO 0);
 signal   m_axis_dout_tvalid :  STD_LOGIC;
 signal   m_axis_dout_tdata :  STD_LOGIC_VECTOR(15 DOWNTO 0);
    
-- Clock period definitions
   constant clk_period : time := 10 ns;
   
begin

	-- Instantiate the Unit Under Test (UUT)
   uut: kaifang0 PORT MAP (
            clk => clk,
            s_axis_cartesian_tvalid => s_axis_cartesian_tvalid,
            s_axis_cartesian_tdata => s_axis_cartesian_tdata,
            m_axis_dout_tvalid => m_axis_dout_tvalid,
            m_axis_dout_tdata => m_axis_dout_tdata
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
     s_axis_cartesian_tvalid <= '0';
     wait for 25ns; 
     s_axis_cartesian_tvalid <= '1';
     s_axis_cartesian_tdata <= X"001008";
     wait for clk_period; 
     s_axis_cartesian_tvalid <= '0';
     wait for clk_period*3; 
     
     s_axis_cartesian_tvalid <= '1';
     s_axis_cartesian_tdata <= X"101008";
     wait for clk_period; 
     s_axis_cartesian_tvalid <= '0';
     wait for clk_period*3; 
     
     s_axis_cartesian_tvalid <= '1';
     s_axis_cartesian_tdata <= X"000008";
     wait for clk_period; 
     s_axis_cartesian_tvalid <= '0';
     wait for clk_period*3; 
     
     wait for clk_period*5; 
      -- insert stimulus here 

      wait;
   end process;
   


end Behavioral;

五、仿真结果

 数据在使能信号有效时输入，在输出使能有效时输出