FSM ps2data

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output [23:0] out_bytes,
    output done); //
    parameter [1:0] b1=2'b00, b2=2'b01, b3=2'b10, d=2'b11;
   reg [1:0] state, next_state;
always @(*) begin
        case(state) 
      b1: next_state <= b2;
      b2:next_state <= b3; 
            b3: if(in[3]==1'b1)
                next_state <= b1;
            else next_state <= d;
            d: if(in[3]==1'b1)
                next_state <= b1;
            else next_state <= d;
    // State transition logic (combinational)
        endcase
end
    
     always @(posedge clk) begin
        if(reset)
            state <= d;
        else
            state <= next_state;
    end // State flip-flops (sequential)
 always @(posedge clk) begin
     if(next_state == b1)begin
         out_bytes[23:16]<=in;
     end
     else if(next_state == b2)begin
         out_bytes[15:8]<=in;
     end
     else if(next_state == b3)begin
         out_bytes[7:0]<=in;
     end
 // FSM from fsm_ps2
 else begin
            out_bytes <= 24'd0;
        end
    end
    
    // Output logic
            assign done = (state == b3);
 
    // New: Datapath to store incoming bytes.
         
endmodule