1.创建ipcore
![创建ipcore](https://i-blog.csdnimg.cn/blog_migrate/524a9e9d3b8993792d00dd69eea8003f.png#pic_center)
2.ipcore设置
![](https://i-blog.csdnimg.cn/blog_migrate/578db8f2525cc33b7bcd263ebd879958.png#pic_center)
3.将创建的ipcore例化到顶层文件
module ex_ipcore(
input wire sclk,
output wire oclk1,
output wire oclk2,
output wire locked
);
pll1 pll1_inst (
.inclk0 ( sclk ),
.c0 ( oclk1 ),
.c1 ( oclk2 ),
.locked ( locked )
);
endmodule
4.测试文件
`timescale 1ns/1ns
module tb_ex_ipcore;
reg sclk;
wire oclk1,oclk2,locked;
initial begin
sclk=0;
end
always #10 sclk = ~sclk;
ex_ipcore ex_ipcore_inst(
.sclk(sclk),
.oclk1(oclk1),
.oclk2(oclk2),
.locked(locked)
);
endmodule
5.自动化仿真文件
quit -sim
.main clear
vlib work
vlog ./tb_ex_ipcore.v
vlog ./altera_lib/*.v
vlog ./../design/*.v
vlog ./../ipcore_dir/PLL1/pll1.v
vsim -voptargs=+acc work.tb_ex_ipcore
add wave tb_ex_ipcore/ex_ipcore_inst/*
run 1us
6.结果图
![](https://i-blog.csdnimg.cn/blog_migrate/b30c802761318beeeb0a26e98332e2e8.png#pic_center)