【约束文件】

约束文件

set_property BITSTREAM.GENERAL.CRC DISABLE [current_design]

set_property PACKAGE_PIN W8  [get_ports ref_clk_clk_p]
create_clock -period 10.000 -name ref_clk_clk_p -waveform {0.000 5.000} [get_ports ref_clk_clk_p]

set_property -dict { PACKAGE_PIN AF14 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports {hdmi_24_data_0[23]}]

set_clock_groups -name async_clock0 -asynchronous -group [get_clocks clk_freerun] -group [get_clocks rxoutclk_out[0]]

set_property DATA_RATE DDR [get_ports exdes_bg3_pin11_50]
#### Need to set diff_std before uncommenting the below line#######
set_property IOSTANDARD LVDS [get_ports exdes_bg3_pin11_50]
set_property LVDS_PRE_EMPHASIS FALSE [get_ports exdes_bg3_pin11_50]

set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *plle*]
##### Use the below mentioned constraints to fix Timing Violations on Bitslice Inputs
#set_property -name CLKOUT0_PHASE -value -90.000 -objects [get_cells *_inst/inst/top_inst/clk_rst_top_inst/clk_scheme_inst/plle3_adv_pll0_inst]
#set_multicycle_path -from [get_clocks -of_objects [get_pins *_inst/inst/top_inst/clk_rst_top_inst/clk_scheme_inst/plle3_adv_pll0_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins *_inst/inst/top_inst/bs_ctrl_top_inst/BITSLICE_CTRL*.bs_ctrl_inst/*_BIT_CTRL_OUT*]] 2
set_property LOC PLLE3_ADV_X0Y4 [get_cells -hier -filter {REF_NAME =~ PLLE*_ADV && NAME =~ *pll0*}]

current_instance core_inst/inst
set_false_path -to [get_pins -hier *sync_flop_0*/D]

set_property PACKAGE_PIN N46 [get_ports clkin_p]
set_property DATA_RATE DDR [get_ports clkin_p]
###### Need to set diff_std before uncommenting the below line
set_property IOSTANDARD LVDS [get_ports clkin_p]

set_property DATA_RATE DDR [get_ports bg1_pin2_15]
########## Need to set diff_std before uncommenting the below line #########
set_property IOSTANDARD LVDS [get_ports bg1_pin2_15]
################## I/O constraints #################
set_property PACKAGE_PIN P49 [get_ports bg1_pin2_15]

################ Rx Equalization constraints ###########
set_property EQUALIZATION EQ_LEVEL0 [get_ports bg0_pin0_0]
set_property DIFF_TERM_ADV TERM_100 [get_ports bg0_pin0_0]

set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]
#####################################

1)以下是将一个BRAM放置在RAMB18_X0Y10的位置，并且将其位置固定。

set_property LOC RAMB18_X0Y10 [get_cells u_ctrl0/ram0]

2)以下是将一个LUT放置到一个切片内的C5LUT BEL的位置，并且将BEL的分配固定。

set_property BEL C5LUT [get_cells u_ctrl0/lut0]

3)以下是将输入总线寄存器放置到ILOGIC单元中。这样做的目的是为了更短输入延迟。

set_property IOB TRUE [get_cells mData_reg*]

4)以下是将两个小的LUT组合到一个LUT6_2中，它使用了O5和O6输出。

set_property LUTNM L0 [get_cell {u_ctrl0/dmux0 u_ctrl0/dmux1}]

5)以下是用于阻止布线器使用第一列的BRAM

#----------------------------------------------------------------------------
set_property LOC SLICE_X0Y47 [get_cells {a0 L0 L1}]
set_property BEL CFF [get_cells a0]
set_property BEL A6LUT [get_cells L0]
set_property BEL B6LUT [get_cells L1]
set_property LOCK_PINS {I1:A4 I0:A2} [get_cells L0]
set_property LOCK_PINS {I1:A3 I0:A2} [get_cells L1]
set_property FIXED_ROUTE {CLBLL_LL_CQ CLBLL_LOGIC_OUTS6 FAN_ALT5 FAN_BOUNCE5  {IMUX_L17 CLBLL_LL_B3} IMUX_L11 CLBLL_LL_A4} [get_nets netA]

#--------------------------------------------------------------------------------```