一、数码管介绍
1、常见数码管:
2、数码管连接方式:
3、共阴、共阳数码管真值表
4、驱动方式:
二、程序设计
1、系统框图:
2、顶层模块
2个子模块:计时器模块、数码管显示模块
3、代码
顶层文件:
module seg_led_top (
input sys_clk,
input sys_rst_n,
output [5:0] sel, //数码管位选定义
output [7:0] seg_led //数码管段选定义
);
parameter TIME_SHOW = 25'd25000_000; //数码管变化的时间间隔0.5s
wire add_flag; //数码管变化的通知信号
//每隔0.5s产生一个时钟周期的脉冲信号
time_count #(.MAX_NUM(TIME_SHOW))
u_time_count(
.clk (sys_clk),
.rst_n (sys_rst_n),
.flag (add_flag)
);
//每当脉冲信号到达时,使数码管显示数量+1
seg_led u_seg_led(
.clk (sys_clk),
.rst_n (sys_rst_n),
.add_flag (add_flag),
.sel (sel),
.seg_led (seg_led)
);
endmodule
计数器主代码
module time_count(
input clk,
input rst_n,
output reg flag
);
parameter MAX_NUM =25000_000;
reg [24:0] cnt;
always @ (posedge clk or negedge rst_n) begin
if (!rst_n) begin
flag <= 1'b0;
cnt <= 24'b0;
end
else if(cnt < MAX_NUM - 1'b1) begin
cnt <= cnt + 1'b1;
flag <= 1'b0;
end
else begin
cnt <= 24'b0;
flag <= 1'b1;
end
end
endmodule
数码管主代码
module seg_led(
input clk,
input rst_n,
input add_flag,
output reg [5:0] sel, //数码管位选定义
output reg [7:0] seg_led //数码管段选定义
);
reg [3:0] num; //数码管显示的十六进制数
//控制数码管位选信号(低电平有效),选中所有的数码管
always @ (posedge clk or negedge rst_n) begin
if(!rst_n)
sel <= 6'b111111;
else
sel <= 6'b000000;
end
//每当通知信号到达时,数码管显示的十六进制数+1
always @ (posedge clk or negedge rst_n) begin
if(!rst_n)
num <= 4'h0;
else if (add_flag) begin
if (num < 4'hf)
num <= num + 1'b1;//累加
else
num <= 4'h0;//清零
end
else
num <= num;
end
//根据数码管显示的数值,控制段选信号
always @ (posedge clk or negedge rst_n) begin
if (!rst_n)
seg_led <= 8'b0;
else begin
case (num)
4'h0 : seg_led <= 8'b1100_0000;
4'h1 : seg_led <= 8'b1111_1001;
4'h2 : seg_led <= 8'b1010_0100;
4'h3 : seg_led <= 8'b1011_0000;
4'h4 : seg_led <= 8'b1001_1001;
4'h5 : seg_led <= 8'b1001_0010;
4'h6 : seg_led <= 8'b1000_0010;
4'h7 : seg_led <= 8'b1111_1000;
4'h8 : seg_led <= 8'b1000_0000;
4'h9 : seg_led <= 8'b1001_0000;
4'ha : seg_led <= 8'b1000_1000;
4'hb : seg_led <= 8'b1000_0011;
4'hc : seg_led <= 8'b1100_0110;
4'hd : seg_led <= 8'b1010_0001;
4'he : seg_led <= 8'b1000_0110;
4'hf : seg_led <= 8'b1000_1110;
default : seg_led <= 8'b1100_0000;
endcase
end
end
endmodule
三、视频演示
FPGA之数码管静态显示