MODELSIM报错合集

(vopt-2697) LSB of part-select into 'MODELSIM报错:(vopt-2697) LSB of part-select into 'S_mult_cos' is out of bounds.' is out of bounds.

原因:位宽没给对

解决方法:将S_mult_cos【29:-16】改为【29-:16】即可

 (vopt-2698) Element index 1 into 'M_coe_paramter' is out of bounds.

原因:该Mcoe_paramter位宽由上层模块输入,上层模块输入的位宽不对

解决方法:将上层模块输入位宽修改正确即可

 

(suppressible): D:\LXLXLX\Vivado\2020.2\data\verilog\src\unisims\BUFG_GT_SYNC.v(46): (vopt-7063) Failed to find 'GRESTORE' in hierarchical name 'glbl.GRESTORE'. #         Region: sim.u_top_layer.u_XINTF_100G_top.IP_INST.cmac_0.inst.BUFG_GT_SYNC】

解决方法:将对应的ip核reset然后重新genereate即可。

# ** Error: ../../../../project_DX5S.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd(82): (vcom-1598) Library "unisim" not found.
# ** Error: ../../../../project_DX5S.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd(82): (vcom-1136) Unknown identifier "<protected>".

解决方法:将vivado生成的库(ip)文件添加到modelsim.ini中

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Mentor, a Siemens business, has unveiled ModelSim 10.7, is unified debug and simulation environment gives today's FPGA designers advanced capabilities in a productive work environment. About Mentor Graphics ModelSim. Modelsim HDL simulator provides FPGA customers with and easy cost-effective way to speed up FPGA development, lab bring up and test. Many FPGA designers go to the lab before adequately vetting their design. This means weeks or even months of inefficient debugging time in the lab. Testing in the lab has limited visibility of the signals in design. It can take 8 hours to do a place and route just instrument additional signals or make a small bug fix. With simulation the debug loop is much faster and there is complete visibility into the signals in the design. Simulation enables a much higher quality FPGA design before entering the lab allowing time spent during lab debug much more productive and focused. In addition to supporting standard HDLs, ModelSim increases design quality and debug productivity. ModelSim’s award-winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design. Its architecture allows platform-independent compile with the outstanding performance of native compiled code. The graphical user interface is powerful, consistent, and intuitive. All windows update automatically following activity in any other window. For example, selecting a design region in the Structure window automatically updates the Source, Signals, Process, and Variables windows. You can edit, recompile, and re-simulate without leaving the ModelSim environment. All user interface operations can be scripted and simulations can run in batch or interactive modes. ModelSim simulates behavioral, RTL, and gate-level code, including VHDL VITAL and Verilog gate libraries, with timing provided by the Standard Delay Format (SDF).

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