使用VHDL设计简单的状态机（Moore型和Mealy型）

首先，让我们简要定义一下Moore和Mealy状态机的差异：

• Moore状态机：在Moore模型中，输出只取决于当前状态。也就是说，对于一个给定的状态，输出总是相同的，无论我们是如何到达该状态的。

• Mealy状态机：在Mealy模型中，输出取决于当前状态以及输入。这意味着，如果当前状态相同，但输入不同，那么输出可能会不同。

现在，我们设计一个简单的Moore和Mealy状态机，它们的功能是检测一个二进制输入序列，并在检测到"110"时产生一个输出信号。

首先是Moore状态机：

library ieee;
use ieee.std_logic_1164.all;

entity moore is
    port (
        clk: in std_logic;
        reset: in std_logic;
        x: in std_logic;
        z: out std_logic
    );
end moore;

architecture behavior of moore is
    type state is (s0, s1, s2);
    signal current_state, next_state: state;
begin
    process (clk, reset)
    begin
        if reset = '1' then
            current_state <= s0;
        elsif rising_edge(clk) then
            current_state <= next_state;
        end if;
    end process;

    process (current_state, x)
    begin
        case current_state is
            when s0 =>
                z <= '0';
                if x = '1' then
                    next_state <= s1;
                else
                    next_state <= s0;
                end if;
            when s1 =>
                z <= '0';
                if x = '1' then
                    next_state <= s2;
                else
                    next_state <= s0;
                end if;
            when s2 =>
                z <= '1';
                if x = '1' then
                    next_state <= s2;
                else
                    next_state <= s0;
                end if;
        end case;
    end process;
end behavior;

接下来是Mealy状态机：

library ieee;
use ieee.std_logic_1164.all;

entity mealy is
    port (
        clk: in std_logic;
        reset: in std_logic;
        x: in std_logic;
        z: out std_logic
    );
end mealy;

architecture behavior of mealy is
    type state is (s0, s1, s2);
    signal current_state, next_state: state;
begin
    process (clk, reset)
    begin
        if reset = '1' then
            current_state <= s0;
        elsif rising_edge(clk) then
            current_state <= next_state;
        end if;
    end process;

    process (current_state, x)
    begin
        case current_state is
            when s0 =>
                z <= '0';
                if x = '1' then
                    next_state <= s1;
                else
                    next_state <= s0;
                end if;
            when s1 =>
                z <= '0';
                if x = '1' then
                    next_state <= s2;
                else
                    next_state <= s0;
                end if;
            when s2 =>
                if x = '1' then
                    next_state <= s2;
                    z <= '0';
                else
                    next_state <= s0;
                    z <= '1';
                end if;
        end case;
    end process;
end behavior;

这两个状态机都是检测二进制序列"110"，当检测到这个序列时，输出信号z为1。但在Moore和Mealy状态机中，输出信号z的行为是有所不同的。在Moore状态机中，当状态达到s2时，z输出为1，而不考虑输入x的值。然而，在Mealy状态机中，只有在状态为s2且输入x为0时，z输出才为1。