HDLBits 4

目录

一、Fsm3

（1）题目

（2）分析+代码 

二、Fsm serial

（1）题目

（2）分析+代码

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前言

状态机练习

 

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一、Fsm3

Fsm3 - HDLBits (01xz.net)

（1）题目

See also: State transition logic for this FSM

The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include an asynchronous reset that resets the FSM to state A.

（2）分析+代码 

1.状态机设计整体思路

   （1）定义状态类型，以及c_st（当前状态），next_state（下一个状态）

   （2）主控时序部分:注意是同步还是异步

   （3）主控时序部分：（输入影响下）状态之间的转换，以及输出

2.reg 定义变量时一定要指定其位宽否则会产生问题。

3.areset为异步时钟信号所有其写法always@(posedge clk or posedge areset)

module top_module(
    input clk,
    input in,
    input areset,
    output reg out); //
    // State transition logic
    parameter A=0,B=1,C=2,D=3;
    reg [1:0]c_st;
    reg [1:0]next_state;
    // State flip-flops with asynchronous reset
    always@(posedge clk or posedge areset)begin 
        if(areset) c_st<=A;
        else c_st<=next_state;
    end
    // Output logic
    always@(*)begin
        case(c_st)
            A:begin out<=0;
                if (in==0) next_state<=A;
                else next_state<=B;
            end
            B:begin out<=0;
                if(in==0) next_state<=C;
                else next_state<=B;
            end
            C:begin out<=0;
                if(in==0) next_state<=A;
                else next_state<=D;
            end
            D:begin out<=1;
                if(in==0) next_state<=C;
                else next_state<=B;
            end
            default:next_state<=A;
        endcase
    end
endmodule

二、Fsm serial

Fsm serial - HDLBits (01xz.net)

（1）题目

In many (older) serial communications protocols, each data byte is sent along with a start bit and a stop bit, to help the receiver delimit bytes from the stream of bits. One common scheme is to use one start bit (0), 8 data bits, and 1 stop bit (1). The line is also at logic 1 when nothing is being transmitted (idle).

Design a finite state machine that will identify when bytes have been correctly received when given a stream of bits. It needs to identify the start bit, wait for all 8 data bits, then verify that the stop bit was correct. If the stop bit does not appear when expected, the FSM must wait until it finds a stop bit before attempting to receive the next byte.

（2）分析+代码

1. 第八位数据输出后in=1,则为stop；in=0时，为？（设其为idle2）

2. idle2：若in为1时，下一状态为idle；若in为0时，下一状态为idle2

3. done：当在的状态为stop时，done=1

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done
); 
    parameter idle=0,start=1,d1=2,d2=3,d3=4,d4=5,d5=6,d6=7,d7=8,d8=9,stop=10,idle2=11;
    reg [3:0] c_st;
    reg [3:0] next_state;
    always@(posedge clk)begin
        if(reset) c_st<=idle;
        else c_st<=next_state;
    end
    always@(*)begin
        case(c_st)
            idle: begin 
                if(in==0) next_state<=start;
                else next_state<=idle;
            end
            start:begin 
                next_state<=d1;
            end
            d1:begin 
                next_state<=d2;
            end
            d2:begin 
                next_state<=d3;
            end
            d3:begin 
                next_state<=d4;
            end
            d4:begin 
                next_state<=d5;
            end
            d5:begin 
                next_state<=d6;
            end
            d6:begin 
                next_state<=d7;
            end
            d7:begin 
                next_state<=d8;
            end
            d8:begin 
                if (in==1)next_state<=stop;
                else next_state<=idle2;
            end
            idle2:begin 
                if(in==1)next_state<=idle;
                else next_state<=idle2;
            end
            stop:begin
                if(in==0)next_state<=start;
                else next_state<=idle;
            end
        endcase
    end
    assign done=(c_st==stop);           
endmodule