module read_tb();
reg clk;
reg rst_n;
reg [23:0] img_in;
wire [23:0] img_out;
parameter sum1=49729; //223*223=49729
parameter sum2=49729; //24025
reg [23:0] data_in_ram[sum1:0]; //in 寄存器组
reg [23:0] data_out_ram[sum1+2:0];
integer i;
integer j;
integer fp_r,fp_w;
always #5 clk=~clk;
//将输入文件数据读取到寄存器组
initial
begin
i=0;
fp_w=$fopen("E:/comp/crop/read_write/data_out.txt","w");
fp_r=$fopen("E:/comp/crop/read_write/data_in.txt","r"); //以读的方式打开文件,用/
while(!$feof(fp_r))begin
$fscanf(fp_r,"%b",data_in_ram[i]) ;//每次读一行,%d 十进制方式
i = i +1;
end
$fclose(fp_r); //关闭文件
$display("read over");
end
//时钟信号与复位信号处理
initial
begin
clk<=0;
rst_n<=0;
#8
rst_n<=1;
end
//数组输入到read模块,模块结果存到data_out_ram
integer counter_1=0,counter_2=0;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
counter_1<=0;
img_in<=24'b0;
end
else if(counter_1<sum1) begin
img_in<=data_in_ram[counter_1];
counter_1<=counter_1+1;
end
else begin
counter_1<=counter_1;
img_in<=24'b0;
end
end
// img_out的处理
reg over=0;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
counter_2=0;
end
else if(counter_2<sum1+2) begin
data_out_ram[counter_2]<=img_out;
counter_2<=counter_2+1;
end
else begin
over<=1;
end
end
// 写入文件[将数组的数据写入文件]
reg w_over=0;
initial begin
wait(over)
fp_w=$fopen("E:/comp/crop/read_write/data_out.txt","w");
for(j=0;j<sum1+2;j=j+1) begin
if((data_out_ram[j]<24'b1111_1111_1111_1111_1111_1111)&&(data_out_ram[j]>0))
begin
$fwrite(fp_w,"%24b ",data_out_ram[j]);
if(j%2==1)
$fwrite(fp_w,"\n");
if(j%223==1)
$fwrite(fp_w,"\n");
end
end
$fclose(fp_w);
w_over<=1;
end
read test(
.clk(clk) ,
.rst_n(rst_n) ,
.img_in(img_in) ,
.img_out(img_out)
);
endmodule
// begin
// $readmemb("E:\comp\M\data_in.txt",data_in_ram);//以二进制逐个读取
// end
Verilog(1):文件读写有关操作
最新推荐文章于 2024-07-22 09:00:00 发布