【xilinx】解决 I/O 时钟布局器错误：UltraScale 示例

于 2024-08-22 12:15:00 发布
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分类专栏： xilinx 文章标签： vivado UltraScale I/O 时钟布局器
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示例详细信息：

设备： xcvu9p-flga2104-2-e
问题：尽管使用 GCIO 引脚作为时钟，但该工具仍返回 I/O Clock Placer 错误

错误：

<span style="background-color:#f3f3f3"><span style="color:#333333"><code>ERROR: [Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets <input_buffer>/O] >
 
    Clock Rule: rule_gclkio_bufg
    Status: FAILED
    Rule Description: An IOB driving a BUFG must use a GCIO in the same clock region as the BUFG
 
    <input_buffer>/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X0Y338 (in SLR 1)
    The loads are distributed to 3 user pblock constraints. In addition, there are 4 loads not in user pblock constraints.
 
    Displaying first 4 loads not in user pblock constraint:
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y161 (in SLR 1)
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y159 (in SLR 1)
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y160 (in SLR 1)
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y162 (in SLR 1)
 
    Displaying the first 10 loads for pblock constraint 1
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y154 (in SLR 1)
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y155 (in SLR 1)
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y167 (in SLR 1)
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y166 (in SLR 1)
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y156 (in SLR 1)
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y165 (in SLR 1)
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y157 (in SLR 1)
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y158 (in SLR 1)
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y164 (in SLR 1)
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y163 (in SLR 1)
 
 
    Displaying the first 1 loads for pblock constraint 2
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y143 (in SLR 1)
 
 
    Displaying the first 1 loads for pblock constraint 3
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y119 (in SLR 0)
 
 
    The above error could possibly be related to other connected instances. Following is a list of
    all the related clock rules and their respective instances.
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y161 (in SLR 1)
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y160 (in SLR 1)
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y162 (in SLR 1)
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y159 (in SLR 1)
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y163 (in SLR 1)
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y164 (in SLR 1)
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y158 (in SLR 1)
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y157 (in SLR 1)
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y165 (in SLR 1)
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y156 (in SLR 1)
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y166 (in SLR 1)
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y167 (in SLR 1)
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y155 (in SLR 1)
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y154 (in SLR 1)
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y143 (in SLR 1)
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y119 (in SLR 0)
 
Resolution: A dedicated routing path between the two can be used if: (a) The global clock-capable IO (GCIO) is placed on a GCIO capable site (b) The BUFG is placed in the same bank of the device as the GCIO pin. Both the above conditions must be met at the same time, else it may lead to longer and less predictable clock insertion delays.
ERROR: [Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets <input_buffer>/O] >
 
    Clock Rule: rule_gclkio_bufg
    Status: FAILED
    Rule Description: An IOB driving a BUFG must use a GCIO in the same clock region as the BUFG
 
    <input_buffer>/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X0Y338 (in SLR 1)
    The loads are distributed to 3 user pblock constraints. In addition, there are 4 loads not in user pblock constraints.
 
    Displaying first 4 loads not in user pblock constraint:
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y224 (in SLR 1)
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y159 (in SLR 1)
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y221 (in SLR 1)
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y218 (in SLR 1)
 
    Displaying the first 10 loads for pblock constraint 1
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y155 (in SLR 1)
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y154 (in SLR 1)
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y153 (in SLR 1)
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y152 (in SLR 1)
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y151 (in SLR 1)
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y144 (in SLR 1)
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y150 (in SLR 1)
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y149 (in SLR 1)
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y146 (in SLR 1)
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y145 (in SLR 1)
 
 
    Displaying the first 1 loads for pblock constraint 2
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y121 (in SLR 1)
 
 
    Displaying the first 1 loads for pblock constraint 3
    <some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y97 (in SLR 0)
 
 
    The above error could possibly be related to other connected instances. Following is a list of
    all the related clock rules and their respective instances.
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y224 (in SLR 1)
 
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y221 (in SLR 1)
 
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y218 (in SLR 1)
 
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y159 (in SLR 1)
 
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y145 (in SLR 1)
 
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y146 (in SLR 1)
 
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y149 (in SLR 1)
 
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y150 (in SLR 1)
 
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y144 (in SLR 1)
 
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y151 (in SLR 1)
 
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y152 (in SLR 1)
 
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y153 (in SLR 1)
 
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y154 (in SLR 1)
 
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y155 (in SLR 1)
 
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y121 (in SLR 1)
 
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y97 (in SLR 0)
 
Resolution: A dedicated routing path between the two can be used if: (a) The global clock-capable IO (GCIO) is placed on a GCIO capable site (b) The BUFG is placed in the same bank of the device as the GCIO pin. Both the above conditions must be met at the same time, else it may lead to longer and less predictable clock insertion delays.
</code></span></span>

这里我们有两个错误与 CLOCK_DEDICATED_ROUTE 约束中提到的同一网络相关。

使用此网络名称，当我们生成网络原理图时，我们可以获取分配给封装引脚 R34 的输入时钟端口。这可以在时钟端口的属性窗口中找到。


然后，示意图显示 17 个 BUFG 由同一端口驱动，其中一些 BUFG 已分配给 PBLOCK。

在放置端口步骤之后，当我们标记这些 BUFG 时，我们可以在设备视图中看到，除了两个之外，所有 BUFG 都放置在同一个时钟区域中，从而遵守规则表中的规则 1。 


在检查异常 BUFG 的约束时，我们发现用户 PBLOCK 强制将这两个放置在 I/O 组旁边的时钟区域之外，因此出现 CDR 错误。


用户 PBLOCK 正在将一个缓冲区分配给下面的时钟区域，并将另一个缓冲区分配给下面的第二个时钟区域。 

这种放置与规则 1 冲突，因此仅从 PBLOCK 中移除 BUFG 是正确的解决方案。没有必要将 BUFG 放入 PBLOCK 中，因为这会造成不必要的限制。

 
在后续运行中，将 BUFG 从 PBLOCK 中移除后，工具在放置过程中不会出错。

检查后发现，所有 BUFG 都被放置在同一个时钟区域，因此遵循规则 1。

 

 

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本文档提供了关于FPGA-MIG和DDR4内存的详细介绍，包括其工作原理、关键信号、以及与之相关的PCB设计准则。DDR4作为目前广泛使用的内存技术，其特点包括高速数据传输和同步工作机制，而FPGA-MIG则为这些内存提供了高效的控制和接口，确保数据传输的稳定性和高效性。文档还详细讨论了DDR4的信号类型，包括时钟信号、地址和命令信号以及数据信号等，这对于理解DDR4的工作机制至关重要。在PCB设计方面，本文档提供了关于如何布线和引脚分配的准则，旨在帮助设计师优化内存与FPGA之间的连接.
pg150-ultrascale-memory-ip.pdf
08-09
Xilinx公司的“pg150-ultrascale-memory-ip.pdf”文档提供了一份关于基于UltraScale架构的FPGA中使用的内存接口IP（Intellectual Property，知识产权）的详细指导手册。本文将详细介绍该文档中所涉及的关键知识点。 ...
01_基于XILINX 7系列FPGA基础入门_美联客XILINXFPGA教程_Xilinx_XILINXFPGA_
10-02
7系列FPGA特别强调了低功耗设计和高速I/O性能。 2. **可编程性**：FPGA的优势在于其灵活性，用户可以通过配置比特流（bitstream）来定义内部逻辑功能，满足各种不同的数字电路设计需求。 ### Xilinx 7系列FPGA特性...
wp275_XILINXFPGA_
10-01
2. **Xilinx FPGA架构**：Xilinx的Virtex、Kintex、Artix等系列产品的特点，包括它们的逻辑单元、I/O接口、嵌入式内存、互连网络等组成部分。 3. **设计流程**：从高层次的系统设计到硬件描述语言（HDL，如Verilog...
pg239-pcie-phy.pdf
02-18
- 作为服务器和工作站中高速 I/O 连接的基础。 **不受支持的功能**： - 特定于 UltraScale 设备的 GTY 不受支持。 - 某些特定的 PCIe 功能可能受限于所选设备的能力。 **许可与订购**： - 需要有效的 Xilinx 许可...
K210 车牌识别项目单片机代码，所用语言为C语言
最新发布
08-24
K210 车牌识别项目单片机代码，所用语言为C语言
源代码-博购企业名录搜索软站留言簿.zip
08-24
源代码-博购企业名录搜索软站留言簿.zip
项目使用华为云_ModelArts_AI_开发平台进行训练部署，
08-24
项目使用华为云_ModelArts_AI_开发平台进行训练部署，采用_Mask_R-CNN_算法模型_ma-mask-rcnn
女弓箭手射箭动画动作：Stylish Archer Assets Pack 1.4
08-24
时尚射手行动包 包括与演示视频相同的角色和武器建模文件。 运动状态已与动画控制器对齐。 产品信息 角色联盟被设置为类人配置。包括5根手指骨、肩臂和腿部扭转骨。 所有动画都包含在内。 弓箭手包总计：454 攻击力：97 移动：38 起立和坐下：4 蹲伏移动：11 蹲下-行走：16 蹲下_行走_瞄准：16 重新加载 : 9 蹲下_瞄准_射击：2 道奇：8 慢跑：20 技能 : 46 步行_目标：16 + 18（版本1.2） 步行：16 装备与解除装备：2 跳跃和双跳：28 空袭：8 移动转身：44 伤害：23 模具：3个 可拆卸：29 （这是原地运动和根运动的总和。）
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