forever 循环语句用法说明 --- verilog HDL

参考：verilog数字系统设计教程【第四版】夏宇闻

1、forever 语句介绍
2、用法要点
3、代码举例

1、forever 语句介绍

连续的执行语句，无限循环。

forever 语句格式
1、单语句
	forever 语句；
2、多语句
	forever 
		begin
			多条语句
		end

2、用法要点：

1)、一般用于仿真：用来产生周期性的波形，作为仿真测试信号。
2)、必须写在 initial 块中。

3、用法举例

`timescale 1ns / 1ps

mudule tb_forever;
//======================================================
/*  forever:
    Generally used for simulation files
*/
//======================================================    
reg clk_always = 0;
reg clk_forever = 0;
reg clk_forever0 = 0;
reg clk_forever1 = 0;
reg clk_forever2 = 0;
reg clk_forever3 = 0;

// always ： Generate a clock with cycle 2
always #1 clk_always = ~clk_always;

// forever 1：Generate a clock with cycle 4
initial begin
    forever #2 clk_forever = ~clk_forever;
end

// forever 2 ：Generate two identical clocks with a cycle of 2
initial begin
    forever begin
        #1  clk_forever0 = ~clk_forever0;
            clk_forever1 = ~clk_forever1;
    end
end

// forever 3 : Generate two clocks with the same cycle but different phase
initial begin
    forever begin
        #1  clk_forever2 = ~clk_forever2;
        #2  clk_forever3 = ~clk_forever3;
    end
end

endmodule

仿真结果如下：