hdlbits.01xz.net /Circuits/Sequential Logic/Finite State Machines/Simple FSM 1(synchronous reset)

这个网站牛逼的点是不像一般教程那样, 先告诉你啥是状态机, 再给你个例程,

是告诉你这样一个功能, 你自己修改实现出来, 最后发现这就是状态机啊.

// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  
    reg out;

    // Fill in state name declarations

    reg present_state, next_state;

    always @(posedge clk) begin
        if (reset) begin  
            present_state = 1;
            out = 1;
        end else begin
            case (present_state)
                // Fill in state transition logic
                0: begin
                    if(in ==0)
                        next_state = 1;
                    else if (in == 1)
                        next_state = 0;
                end
                1: begin
                    if(in ==0)
                        next_state = 0;
                    else if (in == 1)
                        next_state = 1;
                end
            endcase

            // State flip-flops
            present_state = next_state;   

            case (present_state)
                // Fill in output logic
                1: out = 1;
                0: out = 0;
            endcase
        end
    end

endmodule

更新

// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  
    reg out;

    // Fill in state name declarations
    parameter A=1'b0, B=1'b1; 
    
    reg present_state, next_state;

    always @(posedge clk) begin
        if (reset) begin  
            // Fill in reset logic
            next_state = B;
            present_state = B;
            out = B;
        end else begin
            case (present_state)
                // Fill in state transition logic
                A: if(in == 0) next_state = B;
                B: if(in == 0) next_state = A;
                default: next_state = present_state;
            endcase

            // State flip-flops
            present_state = next_state;   

            case (present_state)
                // Fill in output logic
                A: out = A;
                B: out = B;
            endcase
        end
    end

endmodule

不用状态机

// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  
    reg out;

    // Fill in state name declarations

    reg present_state, next_state;

    always @(posedge clk) begin
        if (reset) begin  
            // Fill in reset logic
            out = 1;
        end else begin
            if (in == 0) out = !out; 
        end
    end

endmodule