module top_module (
input clk,
input reset, // Synchronous reset
input s,
input w,
output z
);
parameter A = 8'b00000001;
parameter _XXX = 8'b00000010;
parameter _0XX = 8'b00000100;
parameter _1XX = 8'b00001000;
parameter _00X = 8'b00010000;
parameter _01X = 8'b00100000;
parameter _10X = 8'b01000000;
parameter _11X = 8'b10000000;
reg[7:0] state, next;
//ff
always @(posedge clk) begin
if(reset)
state = A;
else
state = next;
end
//trans
always @(*) begin
next = A;
case (state)
A:begin
if(s == 1)
next = _XXX;
else
next = A;
end
_XXX:begin
if(w == 0)
next = _0XX;
else
next = _1XX;
end
_0XX:begin
if(w == 0)
next = _00X;
else
next = _01X;
end
_1XX:begin
if(w == 0)
next = _10X;
else
next = _11X;
end
_00X:begin
next = _XXX;
end
_01X:begin
next = _XXX;
end
_10X:begin
next = _XXX;
end
_11X:begin
next = _XXX;
end
default:begin
next = A;
end
endcase
end
//out
always @(posedge clk) begin
if(reset)
z = 1'b0;
else begin
case(state)
_00X:begin
//if(w == 1)
z = 1'b0;
//else
//z = 1'b1;
end
_01X:begin
if(w == 1)
z = 1'b1;
else
z = 1'b0;
end
_10X:begin
if(w == 1)
z = 1'b1;
else
z = 1'b0;
end
_11X:begin
if(w == 1)
z = 1'b0;
else
z = 1'b1;
end
default:begin
z = 1'b0;
end
endcase
end
end
endmodule
hdlbits.01xz.net /Circuits/Sequential Logic/Finite State Machines/Q3a:FSM
最新推荐文章于 2024-09-13 16:59:02 发布