RC（Cadence RTL Compiler）物理综合

综合工具，一般有RC和DC；分别来自cadence和synopsys。
综合，又分为逻辑综合（logic synthesis）和物理综合（physical synthesis）；以前只了解逻辑综合，工艺变为28nm后，应该要额外关注物理综合。

参考文档：
RC用户文档里的rc_phys.pdf

逻辑综合和物理综合的区别？

逻辑综合用的线负载模型，叫WLM；是基于pin的fanout建立的。工艺更高级，线延迟占比会越大，比如28nm，就不再适合简单的WLM；因此出现PLE。
物理综合不再简单使用线负载模型，而是使用更准确的物理信息（包括位置），即与布局布线后的线延迟，在RC里叫PLE（Physical Layout Estimation），在DC里叫DC Ultra Topographical。
物理综合与后端的协作性会更贴近，防止出现过度悲观或者过度乐观的设计。

RC提供三种物理综合方法

The simple PLE flow

这个是常用的方法。
利用标准单元和memory库的lef文件，或者PDK里的电容查找表；去得到寄生参数的电阻电容值。然后估算出线长即线延迟。
其中
LEF— The LEF libraries are the physical libraries that contain information such as layer,
via, placement site type, routing design rules, process information, and standard cell and
macro cell definitions.

Capacitance Table— Capacitance tables contain the same type of parasitic
information as the LEF files but the resistance and capacitance information in the
capacitance table is more detailed and therefore more accurate than in the LEF file. The
values in a capacitance table comes from the same process definition files that drive sign
off extraction as well as the various other extractors used in Cadence tools.

原文：
uses technology information and cell areas from the LEF libraries 
instead of from the synthesis technology libraries. The PLE flow uses parasitic resistance and 
capacitance values from the LEF libraries or the capacitance tables (if available) when 
estimating the wire lengths.This flow works in all base RTL Compiler products.

The RC-Spatial flow

好像是指def，即前端根据IP部件划分的面积矩形框，去安排简单的布局。这样与后端布局布线的线延迟参数更切合。
DEF— DEF files are ASCII files that contain information that represent the design at any
point during the layout process. In RTL Compiler, the DEF is primarily used for floorplan
information.

原文：
uses in addition a rapid placement to better estimate long wires in your 
design. This helps deliver more accuracy to the core synthesis optimization engine during 
RTL-to-gate synthesis. This flow works in all base RTL Compiler products, but requires 
access to the Encounter Digital Implementation System.

The RC-Physical flow

这需要后端提供更精确的物理布局布线信息。

原文：
uses in addition a complete placement and considers congestion 
and legal placement as a cost function during the RTL-to-gates phase, to create a better 
netlist. This flow requires an RTL Compiler Advanced Physical Option license inaddition to a 
base RTL Compiler product license and requires access to the Encounter Digital 
Implementation System.

物理综合的相关文件

物理综合的层次信息

simple PLE flow

read lef

In the simple PLE flow, the cellarea defined in the LEF libraries is used instead of the cell
area defined in the timing library (.lib).
The timing library area will be used if
■ The physical libraries do not contain any cell definitions.
■ You onlyread in the technology LEF file (containing only the metal routing layer information without the standard cell/macro definitions).
For best results, always use all available LEF files (standard cell, macro and technology LEF).

相关RC命令

rc:/> set_attribute lef_library {tech.lef cell.lef}
## 注意： 如果分成两句命令定义lef_library，会发生replace的错误。
rc:/> get_attribute lef_library
tech.lef
cell.lef

rc会对lib和lef，针对它们的cell做一致性检查，不一致会report warning。

RTL Compiler will check whether the following definitions are in the LEF file:
■ CAPACITANCE CPERSQ
■ EDGECAPACITANCE
■ RESISTANCE RPERSQ
■ SITE
■ WIDTH

read capacitance或者read QRC

Note:

• If you specify both a capacitance table file and a QRC technology file, the QRC technology file takes precedence.
• It is recommended to specify both LEF and parasitic files. However, you can specify the LEF files only, if the parasiticfiles are not available.
• Scaling factors are used to align a design with a particular process. A capacitance table is process specific where as a scaling factor is design specific. The scaling factors are provided to be consistent with Encounter. Only use a scaling factor if itwill also be used in the back-end.
• For best results, the corner for the parasitic file used should match the corner for the timing library. That is typically max or worst.

The process definition files define layer thicknesses, compositions, and spacings.

For technologies below 28nm, the Encounter Digital Implementation System requires a QRC technology file instead of a capacitance table file.

rc相关命令：

rc:/> set_attribute cap_table_file my.cap
rc:/> set_attribute qrc_tec_file techfile.qrc

RTL Compiler will check if the following information is available inthe parasitic file:
■ PROCESS_VARIATION
■ BASIC_CAP_TABLE
■ width
■ Cc
■ Carea
■ Cfrg

检查或者report PLE信息

rc:/> report ple
============================================================
Generated by: Encounter(R) RTL Compiler 10.1.100
Generated on: Apr 30 2010 03:29:32 pm
Module: DTMF_CHIP
Technology libraries: tsmc18 1.0
tpz973g 230
pllclk 4.3
ram_128x16A 1.1
ram_256x16A 1.1
rom_512x16A 1.1
physical_cells
Operating conditions: slow
Interconnect mode: global
Area mode: physical library
============================================================
Aspect ratio : 1.00
Shrink factor : 1.00
Scale of res/length : 1.00
Scale of cap/length : 1.00
Net derating factor : 1.00
Site size : 5.70 um (from lef [tech+cell])
Capacitance
Layer / Length Data source:
Name Direction Utilization (pF/micron) cap_table_file
------------------------------------------------M1 H 1.00 0.000274
M2 V 1.00 0.000242
M3 H 1.00 0.000242
M4 V 1.00 0.000242
M5 H 1.00 0.000242
M6 V 1.00 0.000304
Resistance
Layer / Length Data source:
Name Direction Utilization (ohm/micron) lef_library
-------------------------------------------------Metal1 H 1.00 0.439130
Metal2 V 1.00 0.360714
Metal3 H 1.00 0.360714
Metal4 V 1.00 0.360714
Metal5 H 1.00 0.360714
Metal6 V 1.00 0.102273
Area
Layer / Length Data source:
Name Direction Utilization (micron) lef_library
-------------------------------------------------Metal1 H 1.00 0.230000
Metal2 V 1.00 0.280000
Metal3 H 1.00 0.280000
Metal4 V 1.00 0.280000
Metal5 H 1.00 0.280000
Metal6 V 1.00 0.440000
rc:/>

合理设置综合模式–interconnect_mode属性

1. 默认interconnect_mode为wire load model；
2. 如果综合flow，吃了lef文件，interconnect_mode会默认改为PLE；
3. 如果吃了lef文件，又想强制改为wire load model。则设置interconnect_mode为wireload；

综上所述，物理综合的话，要检查interconnect_mode的设置；确认应该是PLE。

write_design -encounter

The final part of the physical flow involves exporting the data for place and route processing.
This is done through the write_design -encounter command.
The write_design -encountercommand generates the following files:
■ Netlist (.v)
■ Encounter configuration file (.conf),
■ SDC constraints (.sdc)
■ Tcl script (.enc_setup.tcl)
■ Mode file (.mode)
■ DEF file (.def)
■ Timing derate file (.derate.tcl) — generated when RTL Compiler changed the default timing derate values

Simple PLE Flow的简单脚本

set_attribute source_verbose true /
set_attribute information_level 9 /
suppress_message "xxx"
set_attribute enc_temp_dir rc_enc /
set_attribute lib_search_path path /
set_attribute library "library_list" /
set_attribute lef_library "lef_list"/
set_attribute cap_table_file file/
read_hdl DESIGN/dtmf_chip.v
elaborate DTMF_CHIP
report ple
read_sdc dtmf.sdc
read_def DESIGN/floorplan/dtmf.def
synthesize -to_mapped
report area
report qor
write_design -encounter

WLM的进一步理解

参考文档：
STA（Cadence）——Net delay_长河_新浪博客
http://blog.sina.com.cn/s/blog_436c4cf10101jf1d.html

原文如下：

目标：使用wire-load models来计算net delays，识别用于backannotation的文件格式

Interconnect提供一个具有内部delay的pin to pin 的timing arc，这个delay是由于线的电阻和电容引起的，也称之为wire delay或者net delay。

另外，所有的interconnect arcs都是positively unate。net delay通常是从输入的50%到输出的50%。

wire-delay estimation methods:
(1)Physical layout estimation (PLE): 使用实际的设计和物理库信息，动态计算不同逻辑结构下的线延迟，与布局布线强相关。输入：lef library，capacitance table和floorplan
(2)Wire-load models:wire loads的计算是寄寓最近的calibrated area，选择一个合适的线负载模型是很费力的事情，是一个静态的模型。输入：wire-load models

使用线负载模型(WLM)：net delay = RC (R: net resistance, C: net capcitance)，综合工具根据90%的线的length和fanout，估算出R和C（Poisson distribution）。

Wire loads提供以下信息：几个block sizes和每个的平均capacitance，给丁一个fanout的平均net length（使用Poisson distribution），基于block的面积和net的fanout，计算电容（平均电容乘以net length）。总而言之，STA工具使用静态的WLMs根据长度，fanout和面积来计算net的capacitance。（对于同样的fanout，block的面积越大，估计的平均net length就越长，电容就越大）。

STA工具使用基于面积的wire load选择表来选择合适的线负载模型。

Backannotation:

布局布线之后，收集extracted parasitic（RC）信息，并导入综合工具（或者直接导入，作为parasitics；或者由delay calculator计算出delay，再导入）。这个过程就是backannotation。

Backannotated information is available in the following file formats:
(1) SPEF (standard parasitic exchange format): for extracted parasitics
(2) DSPF (detailed standard parasitic format): for detailed extracted RC
(3) RSPF (reduced standard parasitic format): for less accurate extracted parasitics
(4) SDF (standard delay format): for delay information

Extraction: 布局布线之后计算RC，工具： Cadence QRC，Star RC （Synopsys）
Delay Calculation： 根据RC，准确获取物理net和cell的delays (SDF)，工具：SignalStorm nanometer delay calculator和CeltIC nanometer delay calculator (Cadence).