【FPGA】【Verilog】【基础模块】多路选择器

使用()?():()实现

module mux1(a,b,sel,out );
input a ,b, sel;
output out ;
assign out = sel? a : b;
endmodule 

使用case 实现:

module mux2(out ,a,b,sel);
input a,b,sel;
output out;

reg out;

always @(a or b or sel)
begin 
	case (sel )
		1'b0: out <=  a;
		1'b1:out <= b;
		default: out <= 1'bz;
	endcase 
end
endmodule 
	

使用if else 实现：

module mux3(out ,a ,b,sel);
input a,b,sel;
output out;

reg out ;
always @(a or b or sel )
	begin 
		if(sel )
			out  = a;
		else 
			out  = b;
	end
endmodule