一,CPU0和CPU1上分别跑了自己的程序。这篇文章中我们需要让两个CPU之间能够进行通信,传递数据可以采用DDR或OCM。OCM是一个单端口的存储空间,但是你可以利用ZynqSoC的DMA并行访问OCM其他的交换资源模拟出一个双端口的存储空间。要实现这个机制,访问必须是128位数据对齐,不管在任何情况下都要满足。这个方式能够实现较高的吞吐量,因为DMA可以实现高效的传输大量数据。
二,Key features of the OCM include:
• On-chip 256 KB RAM
• On-chip 128 KB BootROM (not user visible)
• Two AXI 3.0, 64-bit slave interfaces
• Low latency path for CPU/ACP reads to OCM (CPU at 667 MHz – minimum 23 cycles)
• Round-robin pre-arbitration between read and write AXI channels on OCM-interconnect port
(non-CPU port)
• Fixed priority arbitration between the CPU/ACP (via SCU) and OCM-interconnect AXI ports
• Supports full AXI 64-