目录
8. K-map implemented with a multiplexer
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3.Circuits
3.1 Combinational Logic
3.1.2 Multiplexers
1. 2-to-1 multiplexer
Create a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.
module top_module(
input a, b, sel,
output out );
assign out=sel?b:a;
endmodule2. 2-to-1 bus multiplexer
Create a 100-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.
module top_module(
input [99:0] a, b,
input sel,
output [99:0] out );
assign out=sel?b:a;
endmodule3. 9-to-1 multiplexer
Create a 16-bit wide, 9-to-1 multiplexer. sel=0 chooses a, sel=1 chooses b, etc. For the unused cases (sel=9 to 15), set all output bits to '1'.
module top_module(
input [15:0] a, b, c, d, e, f, g, h, i,
input [3:0] sel,
output [15:0] out );
always @(*) begin
case (sel)
4'd0:out=a;
4'd1:out=b;
4'd2:out=c;
4'd3:out=d;
4'd4:out=e;
4'd5:out=f;
4'd6:out=g;
4'd7:out=h;
4'd8:out=i;
default:out=16'hffff;
endcase
end
endmodule4. 256-to-1 multiplexer
Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should select in[0], sel=1 selects bits in[1], sel=2 selects bits in[2], etc.
module top_module(
input [255:0] in,
input [7:0] sel,
output out );
assign out=in[sel];
endmodule5. 256-to-1 4-bit multiplexer
Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all packed into a single 1024-bit input vector. sel=0 should select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc.
//in[sel*4+:4] sel*4+:4 相当于 sel*4+3:sel*4 ，但是这样写不对。
module top_module(
input [1023:0] in,
input [7:0] sel,
output [3:0] out );
assign out=in[sel*4+:4];
endmodule3.1.3 Arithmetic Circuits
1. Half adder
半加器
Create a half adder. A half adder adds two bits (with no carry-in) and produces a sum and carry-out.
module top_module(
input a, b,
output cout, sum );
assign {cout,sum}=a+b;
endmodule
2. Full adder
全加器，输入多了进位。
Create a full adder. A full adder adds three bits (including carry-in) and produces a sum and carry-out.
module top_module(
input a, b, cin,
output cout, sum );
assign {cout,sum}=a+b+cin;
endmodule
3. 3-bit binary adder
Now that you know how to build a full adder, make 3 instances of it to create a 3-bit binary ripple-carry adder. The adder adds two 3-bit numbers and a carry-in to produce a 3-bit sum and carry out. To encourage you to actually instantiate full adders, also output the carry-out from each full adder in the ripple-carry adder. cout[2] is the final carry-out from the last full adder, and is the carry-out you usually see.
module top_module(
input [2:0] a, b,
input cin,
output [2:0] cout,
output [2:0] sum );
assign sum[0]=a[0]^b[0]^cin;
assign sum[1]=a[1]^b[1]^cout[0];
assign sum[2]=a[2]^b[2]^cout[1];
assign cout[0]=(a[0]&b[0]) | (a[0]&cin) | (b[0]&cin);
assign cout[1]=(a[1]&b[1]) | (a[1]&cout[0]) |( b[1]&cout[0]);
assign cout[2]=(a[2]&b[2]) | (a[2]&cout[1]) | (b[2]&cout[1]);
endmodule
4. Adder
module top_module (
input [3:0] x,
input [3:0] y,
output [4:0] sum);
assign sum=x+y;
endmodule5. Signed addition overflow
Assume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0]. These numbers are added to produce s[7:0]. Also compute whether a (signed) overflow has occurred.
溢出只有两种情况：正+正=负，负+负=正，所以就不需要考虑两个输入的符号位不同的情况。
module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
); //
// assign s = ...
// assign overflow = ...
assign s=a+b;
assign overflow=(s[7]&~a[7]&~b[7]) | (~s[7]&b[7]&a[7]);
endmodule
6. 100-bit binary adder
Create a 100-bit binary adder. The adder adds two 100-bit numbers and a carry-in to produce a 100-bit sum and carry out.
module top_module(
input [99:0] a, b,
input cin,
output cout,
output [99:0] sum );
assign {cout,sum}=a+b+cin;
endmodule7. 4-digit BCD adder
You are provided with a BCD (binary-coded decimal) one-digit adder named bcd_fadd that adds two BCD digits and carry-in, and produces a sum and carry-out.
module bcd_fadd {
input [3:0] a,
input [3:0] b,
input cin,
output cout,
output [3:0] sum );
Instantiate 4 copies of bcd_fadd to create a 4-digit BCD ripple-carry adder. Your adder should add two 4-digit BCD numbers (packed into 16-bit vectors) and a carry-in to produce a 4-digit sum and carry out.
module top_module(
input [15:0] a, b,
input cin,
output cout,
output [15:0] sum );
wire [3:0] cc; //连接cin和前一个cout
//实例化第一个模块
bcd_fadd bcd_fadd_inst(
.a (a[3:0]),
.b (b[3:0]),
.cin (cin) ,
.cout (cc[0]) ,
.sum (sum[3:0])
);
//由generate生成的模块
generate
genvar i;
for (i=1;i<4;++i) begin : bcd_fadd1
bcd_fadd bcd_fadd_inst(
.a (a[(7+4*(i-1)):(4+4*(i-1))]),
.b (b[(7+4*(i-1)):(4+4*(i-1))]),
.cin (cc[i-1]),
.cout (cc[i]),
.sum (sum[(7+4*(i-1)):(4+4*(i-1))])
);
end
endgenerate
assign cout = cc[3];
endmodule3.1.4 Karnaugh Map to Circuit
1. 3-variable
module top_module(
input a,
input b,
input c,
output out );
assign out=a|b|c;
endmodule2. 4-variable
module top_module(
input a,
input b,
input c,
input d,
output out );
// assign out=(~b&~c)|(~a&~b&c&~d)|(~a&b&c)|(a&c&d)|(~a&b&~c&~d);
assign out=(~b&~c)|(~a&~d)|(~a&b&c)|(a&c&d);
endmodule
3. 4-variable
根据卡诺图写出公式，并进行化简，得到最简公式，再进行写代码。
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out=((c&~b)|(a&b&c)|(a&~c&~d))?1'b1:((~a&b&~c&~d)|(a&~c&d))?d:1'b0;
endmodule
4. 4-variable
Implement the circuit described by the Karnaugh map below.
Try to simplify the k-map before coding it. Try both product-of-sums and sum-of-products forms. We can't check whether you have the optimal simplification of the k-map. But we can check if your reduction is equivalent, and we can check whether you can translate a k-map into a circuit.
化简半天，没正确，直接写出所有情况了。
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = ~a & b & ~c & ~d | a & ~b & ~c & ~d |
~a & ~b & ~c & d | a & b & ~c & d |
~a & b & c & d | a & ~b & c & d |
~a & ~b & c & ~d | a & b & c & ~d;
endmodule5. Minimum SOP and POS
A single-output digital system with four inputs (a,b,c,d) generates a logic-1 when 2, 7, or 15 appears on the inputs, and a logic-0 when 0, 1, 4, 5, 6, 9, 10, 13, or 14 appears. The input conditions for the numbers 3, 8, 11, and 12 never occur in this system. For example, 7 corresponds to a,b,c,d being set to 0,1,1,1, respectively.
Determine the output out_sop in minimum SOP form, and the output out_pos in minimum POS form.
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
assign out_sop = c & d | ~a & ~b & c;
assign out_pos = ~((~c | ~d) & (a | b | ~c));
endmodule6. Karnaugh map
module top_module (
input [4:1] x,
output f );
assign f=(~x[1]&x[3])|(x[1]&x[2]&~x[3]&x[4]);
endmodule7. Karnaugh map
module top_module (
input [4:1] x,
output f
);
assign f = ~x[1] & x[3] | x[2] & x[3] & x[4] | ~x[2] & ~x[4];
endmodule8. K-map implemented with a multiplexer
按照ab的四种组合进行选择，4选1的四种选择对应的就是mux_in的四位状态。
module top_module (
input c,
input d,
output [3:0] mux_in
);
assign mux_in[0] = c ? 1'b1 : d;
assign mux_in[1] = 1'b0;
assign mux_in[2] = d ? 1'b0 : 1'b1;
assign mux_in[3] = c ? d : 1'b0;
endmodule
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