1.题目
2.源码
// *********************************************************************************
// Project Name : 74381_ALU
// Email : 2972880695@qq.com
// Website : https://home.cnblogs.com/u/hqz68/
// Create Time : 2019/12/10
// File Name : 74381_ALU.v
// Module Name : 74381_ALU
// Abstract :
// editor : sublime text 3
// *********************************************************************************
// Modification History:
// Date By Version Change Description
// -----------------------------------------------------------------------
// 2019/12/10 宏强子 1.0 Original
//
// *********************************************************************************
`timescale 1ns/1ns
module ALU_74381(
//input
input [3:0] A ,
input [3:0] B ,
input [2:0] S ,
//output
output reg [3:0] F
);
//========================================================================\
// =========== Define Parameter and Internal signals ===========
//========================================================================/
localparam Clear = 3'b000 ;
localparam B_A = 3'b001 ;
localparam A_B = 3'b010 ;
localparam ADD = 3'b011 ;
localparam XOR = 3'b100 ;
localparam OR = 3'b101 ;
localparam AND = 3'b110 ;
localparam Preset = 3'b111 ;
//=============================================================================
//**************************** Main Code *******************************
//=============================================================================
always @(S)begin
case(S)
Clear : F = 4'b0000;
B_A : F = B-A;
A_B : F = A-B;
ADD : F = A+B;
XOR : F = A^B;
OR : F = A|B;
AND : F = A&B;
Preset : F = 4'b1111;
endcase
end
endmodule
3.测试平台
`timescale 1ns/1ns
module tb_74381();
reg [3:0] A;
reg [3:0] B;
reg [2:0] S;
wire [3:0] F;
initial begin
S = 3'b000;
A = 4'b1101;
B = 4'b1101;
#100
S = 3'b001;
A = 4'b1001;
B = 4'b1101;
#100
S = 3'b010;
A = 4'b1101;
B = 4'b0101;
#100
S = 3'b011;
A = 4'b1101;
B = 4'b0001;
#100
S = 3'b100;
A = 4'b1100;
B = 4'b0101;
#100
S = 3'b101;
A = 4'b0101;
B = 4'b1001;
#100
S = 3'b110;
A = 4'b1100;
B = 4'b0001;
#100
S = 3'b111;
A = 4'b1101;
B = 4'b0101;
end
ALU_74381 ALU_74381_inst(
//input
.A (A ),
.B (B ),
.S (S ),
//output
.F (F )
);
endmodule
4.仿真波形
欢迎关注我的公众号:芯王国,有更多的FPGA&数字IC的技术分享,还可以获取开源FPGA项目!