4.10.1 主控单元的工作任务
4.10.2 主控单元的状态机设计
程序：
module TX_MCU(PHY_TXSTART,TXSTART_REQ,DATA_CONF,DATA_IN,MAC_CLK,SYS_CLK,
MCU_RST,GLB_RST,PHY_RST,LENGTH,RATE,TXPWR,SHORT_ACK,LONG_ACK,
SIG_ACK,DATA_REQ,DATA_START,DATA_OUT,DATA_DV,FFT_SET,FFT_EN_Q,
RATE_CON,SCRAM_SEED);
input PHY_TXSTART;//发射矢量参数信号，包含数据长度，发射速率和发射功率等，串行输入；
input TXSTART_REQ;//请求发射处理器开始工作信号，与PHY_TXSTART同时拉高21个电平；
input DATA_CONF;//待处理数据输入确认信号，与数据输入同时拉高；
input [7:0] DATA_IN;//待处理数据；
input MAC_CLK;//MAC层数据输入时钟，与工作模式有关，分别为1.25MHz、1.875MHz、2.5MHz、3.75MHz、5MHz、7.5MHz、10MHz、11.25MHz；
input SYS_CLK;//系统时钟，频率为20MHz
input MCU_RST;//异步复位时钟；
input GLB_RST;//全局异步复位时钟；
output PHY_RST;//发射处理器初始化信号；
output [11:0] LENGTH;//待处理数据帧长输出；
output [5:0] RATE;//待处理数据传输速率输出；
output [2:0] TXPWR;//发射机发射功率输出；
output SHORT_ACK;//shotr_generator的工作信号，拉高161个时钟；
output LONG_ACK;//long_generator的工作信号，拉高161个时钟；
output SIG_ACK;//signal_generator的开始工作信号，拉高1个时钟
output DATA_REQ;//向上位机接口模块发送的数据传输请求信号，依SIG_ACK拉高一个时钟；
output DATA_START;//Data_generator开始工作信号，比第一个符号的数据送入提前两个周期，拉高一个时钟；
output [7:0] DATA_OUT;//待处理数据输出，输出至Data_generator;
output DATA_DV;//待处理信号输出有效端口，随数据输出同步拉高；
output FFT_SET;//FFTpro初始化信号，完成FFTpro模式配置工作；
output FFT_EN_Q;//FFTpro处理开始信号，触发一个符号数据的IFFT变换
output [3:0] RATE_CON;//Data_generator所需的传输速率控制信号，用于对数据编码与调制的控制；
output [6:0] SCRAM_SEED;//Data_generator的扰码器所需的移位寄存器初始化向量；
wire [4:0] TXPAR_BUFADDR; //transmit parameters buffer address signal
wire THRESH1; //transmit parameters buffer over signal
wire [8:0] MCOUNTER; //U_MAIN_COUNTER outputs
wire [6:0] COUNT80; //U_COUNT80 outputs
wire FFT_EN; //signal for FFT transform starting
wire [4:0] COUNT_DATA; //U_COUNT_DATA outputs
wire DATA_TXSTART; //the signal for starting the DATA field transmission
wire [4:0] COUNT30; //U_COUNT30 outputs
wire REQ; //the signal asking for the Data Octs from MAC
wire GLB_RST_H; //Reset signal for IP core U_TXPAR_BUFADDR
wire RST; //Reset signal for IP cores except U_TXPAR_BUFADDR
reg [20:0] TXPAR_BUF; //transmit parameters buffer
reg PHY_RST; //transmit initialize signal
reg [11:0] LENGTH; //transmit parameters: data length
reg [5:0] RATE; //transmit parameters: data rate
reg [2:0] TXPWR; //transmit parameters: transmit power
reg MCOUNTER_CE; //U_MAIN_COUNTER enable signal
reg BUF_OVER; //The register for the transmit parameters buffer over signal
reg SHORT_ACK; //short sequences transmission start signal
reg LONG_ACK; //Long sequences transmission enable signal
reg SIG_ACK; //Signal field process start signal
reg FFT_SET; //FFTPro module initialize signal
reg COUNT80_CE; //U_COUNT80 enable signal
reg FFT_EN_Q; //register of signal FFT_EN
reg [13:0] N_SYM_FFT; //Counter for the number of symbols to help generate FFT_EN signal, add one bit as the sign bit
reg COUNT_DATA_CE; //U_COUNT_DATA enable signal
reg COUNT30_CE; //U_COUNT30 enable signal
reg [13:0] N_SYM_DATA; //Counter for the number of symbols to help generate DATA_REQ signal, add one bit as the sign bit
reg DATA_REQ; //Register for signal REQ
reg [7:0] DATA_BUF; //The input buffer for DATA_IN
reg DATA_RDY; //The signal indicationg that DATA have been inputted
reg DATA_START; //The signal enable DATA_generator
reg [7:0] DATA_OUT; //DATA output register
reg DATA_DV; //The signal indicationg DATA valid
reg RST_CON; //The signal helping generate PHY_RST
reg [3:0] RATE_CON; //RATE_CON is used for DATA_generator to control its coding and mapping
reg [6:0] SCRAM_SEED; //The signal for scrambler of DATA_generator to initialize its LSFR
reg FFT_EN_Q1;
reg SHORT_ACK1;
assign GLB_RST_H=~GLB_RST;
assign RST=~MCU_RST;
//TXSTART_REQ is enabled to convert the transmitter into transmit state.
//The transmit parameters are buffered.
//counter for buffer addresses generation
counter21 U_TXPAR_BUFADDR (
.Q(TXPAR_BUFADDR), //transmit parameters buffer address signal
.CLK(MAC_CLK),
.THRESH0(THRESH1), //transmit parameters buffer over signal
.CE(TXSTART_REQ),
.SCLR(GLB_RST_H));
//initialize PHY_RST，LENGTH，RATE，TXPWR
always @ (negedge GLB_RST or posedge MAC_CLK)
if (!GLB_RST) //These signals can only be reset by the global reset
begin //signal but not PHY_RST.
TXPAR_BUF<=0; //transmit parameters buffer（12bits LENGTH ；6bits RATE；3bits TXPWR；）
PHY_RST<=1; //transmit initialize signal
RST_CON<=0; //The signal helping generate PHY_RST
BUF_OVER<=0; //The register for the transmit parameters buffer over signal
LENGTH<=0; //transmit parameters: data length
RATE<=0; //transmit parameters: data rate
TXPWR<=0; //transmit parameters: transmit power
end
else
begin
if (TXSTART_REQ) //transmit parameters are buffered into TXPAR_BUF by
begin //control of TXSTART_REQ
TXPAR_BUF[TXPAR_BUFADDR]<=PHY_TXSTART;//21bits的PHY_TXSTART装载到TXPAR_BUF；
end
if (TXSTART_REQ && !RST_CON) //RST_CON will be set 1 to prevent PHY_RST from getting low again
begin
PHY_RST<=0; //transmit initialize
RST_CON<=1;
end
else if (!TXSTART_REQ)
RST_CON<=0;
if (!PHY_RST) //PHY_RST gets low(valid) for 1 clock
PHY_RST<=1;
if (THRESH1) //transmit parameters buffer over signal（21）
BUF_OVER<=1; //The register for the transmit parameters buffer over signal
else
BUF_OVER<=0;
if (BUF_OVER) //BUF_OVER will get high for one clock after transmit
begin //parameters are buffered.
LENGTH<=TXPAR_BUF[20:9]; //Transmit parameters will be put out by the control of
RATE<=TXPAR_BUF[8:3]; //BUF_OVER
TXPWR<=TXPAR_BUF[2:0];
end
else if (!TXSTART_REQ)
TXPAR_BUF<=0; //When output is finished, TXPAR_BUF will be cleared.
end
//transmit control signals generation and output
//The main counter for transmit sequences （320计数器）
main_counter U_MAIN_COUNTER (
.Q(MCOUNTER), //U_MAIN_COUNTER outputs
.CLK(SYS_CLK),
.CE(MCOUNTER_CE), //U_MAIN_COUNTER enable signal
.SCLR(RST));
//The counter to generate FFT_EN signals
counter_80 U_COUNT80 (
.Q(COUNT80), //U_COUNT80 outputs
.CLK(SYS_CLK),
.THRESH0(FFT_EN),
.CE(COUNT80_CE),
.SCLR(RST));
always @ (negedge MCU_RST or posedge SYS_CLK)
if (!MCU_RST)
begin
MCOUNTER_CE<=0;
N_SYM_FFT<=0; //Counter for the number of symbols to help generate FFT_EN signal, add one bit as the sign bit
SHORT_ACK<=0;
LONG_ACK<=0;
SIG_ACK<=0;
FFT_SET<=0;
COUNT80_CE<=0;
FFT_EN_Q<=0; //FFTpro处理开始信号，触发一个符号数据的IFFT变换
FFT_EN_Q1<=0;
SCRAM_SEED<=0; //Data_generator的扰码器所需的移位寄存器初始化向量；
RATE_CON<=0; //Data_generator所需的传输速率控制信号，用于对数据编码与调制的控制；
end
else
begin
if (BUF_OVER) //if BUF_OVER is enabled, the U_MAIN_COUNTER will be started
begin //as well as the transmission of short sequences
MCOUNTER_CE<=1;
SHORT_ACK1<=1;
N_SYM_FFT<=TXPAR_BUF[20:9]+21; //？？？？
//N_SYM_FFT will be set the number of length, add 21 for the service field,
//tail bits and signal field (2.75+18).
SCRAM_SEED<=7'b1011101;
//数据速率（6、9、12、18、24、36、48、54）；参考Rate域的内容及相应的调制方式表格（P46）
case (TXPAR_BUF[8:3]) // RATE_CON is from the vector of RATE.
6'd6 : RATE_CON<=4'b1101 ;
6'd9 : RATE_CON<=4'b1111 ;
6'd12: RATE_CON<=4'b0101 ;
6'd18: RATE_CON<=4'b0111 ;
6'd24: RATE_CON<=4'b1001 ;
6'd36: RATE_CON<=4'b1011 ;
6'd48: RATE_CON<=4'b0010 ;
6'd54: RATE_CON<=4'b0011 ;
default: RATE_CON<=4'b0000 ;
endcase
end
if(SHORT_ACK1)
SHORT_ACK1<=~SHORT_ACK1;
if (SHORT_ACK1)
SHORT_ACK<=1;
if (MCOUNTER==161) //"MCOUNTER==160" can stop the short sequences transmission
SHORT_ACK<=0;
if (MCOUNTER==160) //When MCOUNTER equals to 159, long sequences will begin to transmit
LONG_ACK<=1; //and stop after 161 clocks.
if (MCOUNTER==321) //When MCOUNTER==320, the task of U_MAIN_COUNTER will be finished.
begin //LONG_ACK will be also get low.
MCOUNTER_CE<=0;
LONG_ACK<=0;
end
if (MCOUNTER==42) //MCOUNTER==42？？？ can enable the SIG_ACK which will be high for 1 clock
SIG_ACK<=1;
else if (SIG_ACK)
SIG_ACK<=~SIG_ACK;
if (MCOUNTER==116) //MCOUNTER==116 will initialize the FFTpro module to make it ready for
begin //process. U_COUNT80 will also be started for the output of FFT_EN. At
FFT_SET<=1; //the same time, the task of U_MAIN_COUNTER will be finished
COUNT80_CE<=1;
end
else if (FFT_SET)
FFT_SET<=~FFT_SET;
if (FFT_EN) //The FFT_EN is set into FFT_EN_Q and N_SYM_FFT is decreased by 18
begin
FFT_EN_Q1<=1;
N_SYM_FFT<=N_SYM_FFT-18;
end
else
FFT_EN_Q1<=0;
if(FFT_EN_Q1)
FFT_EN_Q<=1;
else if(FFT_EN_Q)
FFT_EN_Q<=~FFT_EN_Q;
if (N_SYM_FFT==0 || N_SYM_FFT[13]==1'b1) //If the N_SYM_FFT<=0, all the data have been transmitted, so U_COUNT80 will
COUNT80_CE<=0; //be stopped.
end
//Generation of the signal DATA_REQ and completion of the DATA output
//Notice: It works by clock MAC_CLK, so it will be descripped
//in another always block.
counter_data U_COUNT_DATA ( //Counter for starting the DATA filed transmission
.Q(COUNT_DATA),
.CLK(MAC_CLK),
.THRESH0(DATA_TXSTART),
.CE(COUNT_DATA_CE),
.SCLR(RST));
counter_30 U_COUNT30 ( //The counter to generate DATA_REQ signals
.Q(COUNT30),
.CLK(MAC_CLK),
.THRESH0(REQ),
.CE(COUNT30_CE),
.SCLR(RST));
always @ (negedge MCU_RST or posedge MAC_CLK)
if (!MCU_RST)
begin
COUNT_DATA_CE<=0;
N_SYM_DATA<=0;
COUNT30_CE<=0;
DATA_REQ<=0;
DATA_BUF<=0;
DATA_RDY<=0;
DATA_START<=0;
DATA_OUT<=0;
DATA_DV<=0;
end
else
begin
if (BUF_OVER) //U_COUNT_DATA is started by BUF_OVER. After counting 30 clocks,
begin //DATA_REQ generation will be started.
COUNT_DATA_CE<=1;
N_SYM_DATA<=TXPAR_BUF[20:9]+3; //N_SYM_DATA will be also initialized. //字节数
end
if (DATA_TXSTART) //When DATA_TXSTART is high, COUNT30_CE will be started to
COUNT30_CE<=1; //generate the signal of DATA_REQ.
if (COUNT_DATA==30) //When COUNT_DATA equals to 30, U_COUNT_DATA will be stopped and
begin //the signal DATA_START will be also get high for 1 clock to
COUNT_DATA_CE<=0; //start DATA_generator.
DATA_START<=1;
end
if (DATA_START==1)
DATA_START<=~DATA_START;
if (REQ) //REQ signal from U_COUNT30 will be output. At the same time,
begin //N_SYM_DATA will be decreased by 18 to count the data num.
DATA_REQ<=1;
N_SYM_DATA<=N_SYM_DATA-18;
end
else
DATA_REQ<=0;
if (N_SYM_DATA==0 || N_SYM_DATA[13]==1'b1) //If the N_SYM_DATA<=0, all the data have been transmitted,
COUNT30_CE<=0; //so U_COUNT80 will be stopped
if (DATA_CONF) //DATA input will be buffered with the control of input signal
begin //DATA_CONF and the DATA_RDY will be get enabled to indicate
DATA_BUF<=DATA_IN; //DATA output can be started.
DATA_RDY<=1;
end
else
begin
DATA_BUF<=0;
DATA_RDY<=0;
end
if (DATA_RDY) //If the DATA_RDY is high, DATA will be outputted.
begin
DATA_OUT<=DATA_BUF;
DATA_DV<=1;
end
else
begin
DATA_OUT<=0;
DATA_DV<=0;
end
end
endmodule仿真图形：
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