3分频 50%占空比
方法:分别用clk的上升沿和下降沿得到占空比为1/3的时钟,然后相或
module 3_div(
input clk,
input rst,
input clk_div
);
reg [2:0] cnt;
wire clk_p;
wire clk_n;
always@(posedge clk or negedge rst)
begin
if(!rst)
cnt<=0;
else if(cnt==2)
cnt<=0;
else
cnt<=cnt+1;
end
//上升沿采样上述时钟
always@(posedge clk or negedge rst)
begin
if(!rst)
clk_p<=0;
else if(cnt==1)
clk_p<=~clk_p;
else if(cnt==2)
clk_p<=~clk_p;
else
clk_p<=clk_p;
end
//下降沿采样上述时钟
always@(negedge clk or negedge rst)
begin
if(!rst)
clk_n<=0;
else
clk_n<=clk_p;
end
//产生分频时钟
assign clk_div<=clk_n | clk_p;
endmodule
仿真代码
module 3_div_tb;
reg clk;
reg rst;
wire clk_div;
initial begin
clk = 0;
rst = 0;
#100;
rst = 1;
#20000;
end
always #2 clk = ~clk;
3_div u0(
.clk(clk),
.rst(rst),
.clk_div(clk_div);
endmodule