Hardware ---xilinx vivado的Combinatorial Loop Alert

最新推荐文章于 2024-03-21 15:46:19 发布

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最新推荐文章于 2024-03-21 15:46:19 发布

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在Xilinx Vivado设计中遇到DRC LUTLP-1警告，提示存在组合逻辑环路可能导致race condition和时序分析不准确。解决方法是在XDC文件中为环路中的网路设置ALLOW_COMBINATORIAL_LOOPS属性为TRUE，并调整相关细胞的约束。通过设置特定的XDC命令，可以消除警告并确保设计的正确性。

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问题描述

[DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: ‘set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]’. One net in the loop is write_read_top/u_sdram_controller/wr_cnt[3]_i_5_n_0. Please evaluate your design. The cells in the loop are: write_read_top/u_sdram_controller/wr_cnt[3]_i_5.

解决办法

再xdc中添加如下的约束：

set_property ALLOW_COMBINATORIAL_LOOPS true [get_nets -of_objects [get_cells write_read_top/u_sdram_controller/main_state[3]_i_16]]
set_property ALLOW_COMBINATORIAL_LOOPS true [get_nets -of_objects [get