VIVADO中ILA抓取三段式状态机中组合逻辑信号注意事项

抓取三段式状态机中组合逻辑信号会出现以下错误！

 [DRC LUTLP-1] Combinatorial Loop Alert: 2 LUT cells form a combinatorial loop.

        使用ILA抓取三段式状态机中，组合逻辑的 RdState 和 NxtRdState，NxtRdState出现如下错误

        This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'. One net in the loop is u_DdrRdData/NxtRdState[0]. Please evaluate your design. The cells in the loop are: u_DdrRdData/NxtRdState_inferred_i_3, and u_DdrRdData/NxtRdState_inferred_i_8.

        组合循环是组合逻辑，它在没有寄存器的情况下反馈给自身。 最简单的例子是一个反相器，它的输出反馈到输入，从而产生一个振荡器。

        组合逻辑代码中的输出拿去当输入了，从而产生了竞争

         解决方法：可使用assign对组合逻辑中的NxtRdState赋值给另一变量，使用另一变量在ILA中抓取NxtRdState的状态。