- 并转串(4bit)
module pal_ser(
input clk,
input rst_n,
input load
input [3:0]din,
output dout);
reg [3:0] databuff;
always @(posedge clk or negedge rst_n)
if(!rst_n) databuff <= 4'b0;
else if
module pal_ser(
input clk,
input rst_n,
input load
input [3:0]din,
output dout);
reg [3:0] databuff;
always @(posedge clk or negedge rst_n)
if(!rst_n) databuff <= 4'b0;
else if