- 同步设计
module synFIFO(
input clk,rst_n,rd,wr,
input [7:0] data_in,
output [7:0] data_out,
output full,empty
);
reg [15:0] data_out;
reg [7:0] mem [15:0];
reg [3:0]rdp,wrp;
// mem + write pointer
always @(posedge clk)
if(!rst) wrp <= 0;
else (wr && !full) begin
wrp <= wrp + 1;
mem[wrp] <= data_in; end
// read pointer + data out
always @(posedge clk)
if(!rst) begin
rdp <= 0;
data_out <=