verillog generate

verillog generate for logic

module test(bin,gray); 

       parameter SIZE=8; 

       output [SIZE-1:0] bin; 

       input [SIZE-1:0] gray; 

       genvar i; //genvar i;也可以定义到generate语句里面 

       generate 

              for(i=0;i<SIZE;i=i+1) 

              begin:bit 

                     assign bin[i]=^gray[SIZE-1:i]; 

              end 

       endgenerate 

endmodule  

verillog generate for module

generate 
genvar i; //generate 8 samll fifo for in_data[i] 8X72 
   for(i=0; i<NUM_QUEUES; i=i+1) begin: in_arb_queues //NUM_QUEUES = 8 
   small_fifo 
       #(
       .WIDTH                    (DATA_WIDTH+CTRL_WIDTH), 
       .MAX_DEPTH_BITS           (2                    )) 
   in_arb_fifo 
       (// Outputs 
       .dout                     ({fifo_out_ctrl[i], fifo_out_data[i]}), 
       .full                     (                     ), 
       .nearly_full              (nearly_full[i]       ), 
       .prog_full                (                     ), 
       .empty                    (empty[i]             ), 
       // Inputs 
       .din                      ({in_ctrl[i], in_data[i]}), 
       .wr_en                    (in_wr[i]             ), 
       .rd_en                    (rd_en[i]             ), 
       .reset                    (reset                ), 
       .clk                      (clk                  ));                                                                   
   end 
endgenerate 

verilog generate if

 generate
      if (<condition>) begin: <label_1>
         <code>;
      end else if (<condition>) begin: <label_2>
         <code>;
      end else begin: <label_3>
         <code>;
      end
   endgenerate