Fsm hdlc

Fsm hdlc

module top_module(
    input clk,
    input reset,    // Synchronous reset
    input in,
    output disc,
    output flag,
    output err);
    parameter IDLE=4'd0,RXD=4'd1,DISC_F=4'd2,FLAG_F=4'd3,ERR_F=4'd4,
    RXD1=4'd5;
    reg [3:0] current_state,next_state;
    reg [3:0] cnt_reg;
    always @(posedge clk) begin
        if(reset)
            current_state<=IDLE;
        else
            current_state<=next_state;
    end
    
    always @(*) begin
        case(current_state)
            IDLE:next_state=in?RXD:IDLE;
            
            RXD:next_state=(cnt_reg==5)?((in==0)?DISC_F:RXD1):RXD;
            DISC_F:next_state=(in==0)?IDLE:RXD;
            
            RXD1:next_state=(in==0)?FLAG_F:ERR_F;
            FLAG_F:next_state=(in==0)?IDLE:RXD;
            
            ERR_F:next_state=(in==0)?IDLE:ERR_F;
            default:next_state=IDLE;
        endcase	
    end
    
    always @(posedge clk) begin
        if(reset)
             cnt_reg<=0;
        else if(next_state==RXD)
            begin
                if(in)
                    cnt_reg<=cnt_reg+1;
                else
                     cnt_reg<=0;
            end
        else
            cnt_reg<=0;
    end
    

    assign disc=(current_state==DISC_F);
    assign flag=(current_state==FLAG_F);
    assign err=(current_state==ERR_F);
endmodule