轮询仲裁器

轮询仲裁器：每次访问结束后都会更新优先级；假设有四个请求A，B，C，D，某个时刻这4个请求的优先级为A>B>C>D，这个时刻将总线控制权交给C，则这个请求后的优先级修改为D>A>B>C，代码中以3请求为例：
上代码:
bus_arbitor:

module bus_arbitor(
    input wire clk,
    input wire rstn,
    input wire singal_1,
    input wire singal_2,
    input wire singal_3,
//    input wire singal_4,
    output reg [2:0] out_signal,//[1,2,3]
    output reg [1:0] current_arb
);
parameter S1=2'b01;
parameter S2=2'b10;
parameter S3=2'b11;
parameter NULL=2'b00;
//reg [1:0]current_arb;
reg [1:0]last_arb;

always @(posedge clk or negedge rstn) begin
    if(~rstn) begin
        current_arb<='b0;
        last_arb<='b0;
    end
    else begin
        case({singal_1,singal_2,singal_3})
            3'b000:begin
                current_arb<='b0;
                last_arb<='b0;
            end
            3'b001:begin
                current_arb<=S3;
                last_arb<=S3;
            end
            3'b010:begin
                current_arb<=S2;
                last_arb<=S2;
            end
            3'b100:begin
                current_arb<=S1;
                last_arb<=S1;
            end
            3'b011:begin
                case(last_arb)
                S1:begin current_arb<=S2; last_arb<=S2;end
                S2:begin current_arb<=S3; last_arb<=S3;end
                S3:begin current_arb<=S2; last_arb<=S2;end
                endcase
            end
            3'b101:begin
                case(last_arb)
                S1:begin current_arb<=S3; last_arb<=S3;end
                S2:begin current_arb<=S3; last_arb<=S3;end
                S3:begin current_arb<=S1; last_arb<=S1;end
                endcase
            end
            3'b110:begin
                case(last_arb)
                S1:begin current_arb<=S2; last_arb<=S2;end
                S2:begin current_arb<=S1; last_arb<=S1;end
                S3:begin current_arb<=S1; last_arb<=S1;end
                endcase
            end
            3'b111:begin
                case(last_arb)
                S1:begin current_arb<=S2; last_arb<=S2;end
                S2:begin current_arb<=S3; last_arb<=S3;end
                S3:begin current_arb<=S1; last_arb<=S1;end
                endcase
            end
            default:begin
                current_arb<=NULL;
                last_arb<=last_arb;
            end
        endcase
    end
end

always @(*) 
    case(current_arb)
        S1:begin out_signal=3'b100;end
        S2:begin out_signal=3'b010;end
        S3:begin out_signal=3'b001;end
        default:out_signal=3'b000;
    endcase
endmodule

tb:

`timescale  1ns/1ps
module tb_ar();
reg clk;
reg rstn;
reg singal_1;
reg singal_2;
reg singal_3;
//    input wire singal_4,
wire [2:0]out_signal;//[1,2,3]
wire current_arb;
parameter perd = 20;
initial begin
    rstn=1;
    clk=1;
    #20 rstn =0;
    #20 rstn =1;
end

always #(perd/2) clk =~clk;
initial begin
    singal_1=0;singal_2=0;singal_3=0;
    #85 singal_2=1;
    #20 singal_1=1;singal_2=0;singal_3=1;

end



bus_arbitor bus_arbitor_inst( 
    .clk(clk),
    .rstn(rstn),
    .singal_1(singal_1),
    .singal_2(singal_2),
    .singal_3(singal_3),
//    input wire singal_4,
    .out_signal(out_signal),//[1,2,3]
    .current_arb(current_arb)
);

endmodule